臺灣博碩士論文加值系統

近年來AC-3與MPEG已經成功的被應用到各種消費性產品上，尤其是各種數位視訊音樂CD、視訊的傳播。本篇論文介紹一顆單晶片提供一個提供一個共通的可完成AC-3與MPEG頻域時域轉換的共通硬體架構。這個架構使用了快速傅立葉轉換 (Fast Fourier transform) 的核心和一些額外的twiddle factor乘法及一些內部的隨機存取記憶體 (Random access memory) 來完成AC-3 與 MPEG的IMDCT。這個快速傅立葉轉換核心使用的是Split-radix 2/4/8 Algorithm。此結構為pipeline架構，適合處理8n點的FFT，只需將n個PE串接即可。這顆chip使用0.35um製程，面積是5400 um2。

The (MPEG) and Digital Audio Compression-3 (AC-3) audio standards have been adapted successfully into several promising consumer applications, notably digital videodisc and digital audio broadcast. This thesis introduce a single chip which have a common hardware engine that performs he frequency to time domain transform for both MPEG and Dolby AC-3 audio standards. The structure consists of the real fast Fourier transform (FFT) core with some additional multiplier unit and random access memory to do inverse modified cosine transform (IMDCT) in AC-3 and MPEG. The FFT core is implemented based on split-radix 2/4/8 algorithm. This architecture is pipeline structure and can be easily used on 8n-point FFT by adding n “PEs” (processing unit). The chip use 0.35 um process and its area is 5400 um2.

ABSTRACT (in Chinese) I
ABSTRACT (in English) II
AKNOWLEGDEMENT III
CONTENTS IV
LIST OF FIGURES VI
LIST OF TABLES IX
CHAPTER 1 INTRODUCTION
1.1 Motivation 1
CHAPTER 2 AN OVERVIEW OF DELTA-SIGMA CONVERTERS
2.1 Introduction 3
2.2 AC-3 Overview 3
2.3 AC-3 Coding System 4
2.3.1 AC-3 bit stream feature 6
2.4 Decoder Implementation Strategy 7
2.4.1 Decoder synchronization timing 8
2.4.2 Decoding input processing 9
2.4.3 Decoder output processing 12
2.5 MPEG Audio Coding 13
2.5.1 Overview 14
2.5.2 Specification 15
2.5.3 Decoding flow chart 16
CHAPTER 3 SUB-BAND FILTER BANK AND MDCT/IMDCT IN AC-3 AND MPEG
3.1 Introduction 18
3.2 Time Domain Aliasing Cancellation 19
3.3 Modified DCT in AC-3 22
3.4 The MDCT Algorithm using FFT 24
3.4.1 Fast implementation of MDCT 25
3.4.1.1 Long transform (Block switch is OFF) 25
3.4.1.2 Short transform for the first block 29
3.4.1.3 Short transform for the second block 29
3.5 The MPEG MDCT Algorithm Using FFT 30
CHAPTER 4 CHIP ARCHITECTURE
4.1 Fourier Transform Core 34
4.1.1 Split-radix FFT 34
4.1.2 Radix 2/8 algorithm 37
4.1.3 Split-radix 2/4/8 algorithm 40
4.1.4 FFT pipeline architecture 42
4.2 Twiddle Factor Generator 42
4.3 Complex Multiplications by WN/8, W3N/8 46
4.4 Delay consideration 47
4.5 Memory Organization 50
4.6 Controller signals 53
4.7 Chip Architecture Overview 54
4.8 Schematics 55
4.9 Simulation Results 60
CHAPTER 5 CONCLUSION
5.1 Conclusion 69
REFERENCES 71

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