臺灣博碩士論文加值系統

隨著CMOS電晶體通道長度的縮小，設計出一個低價、 低功率、 高度整合的晶片已成為一種趨勢。 因此， 本論文設計一個外差式接收器的CMOS RF前級。此接收器包含低雜訊放大器，兩個混頻器，和電壓控制振盪器。 我們使用單端低雜訊放大器和雙端混頻器，以獲得較好的線性特性。 此單端低雜訊放大器提供14.8 dB增益， 9.1 dBm IIP3， 和 1.3 dB雜訊因素。 而第一個混頻器則提供12.3 dB轉換增益， 20.4 dB的雜訊因素， 和-2.4 dBm IIP3。第二個混頻器提供 11.67 dB 轉換增益， 3.41的雜訊因素， 和-5.45 dBm IIP3。 此電壓控制振盪器在600KHz偏移頻率的相位雜訊為-100 dBc， 且其調整靈敏度為73.6MHz/V。 此電路是用安捷倫EEsoft EDA-RFIC及TSMC 0.35 μm CMOS製程參數模擬， 且結果顯示整體的雜訊因素為2.7456 dB、 -1.2 dBm IIP3、和148.17 mW功率消耗。

With the scaling down of CMOS technology, it has became a new trend to design a CMOS IC with low cost, low power and high integration. Therefore, a CMOS RF front-end for a heterodyne receiver is designed in this thesis. The front-end circuit includes an LNA, two mixers and a VCO. In order to have a better linearity, a single-ended LNA and double-balanced mixers are employed. The single-ended LNA provides 14.8 dB Gain, 9.1 dBm IIP3, and 1.3 dB noise figure. The first mixer provides 12.3 dB conversion gain, 20.4dB noise figure, and —2.4dBm IIP3. The second mixer provides 11.7dB conversion gain, 23.4dB noise figure, and —5.5dBm IIP3. The VCO has —100 dBc phase noise at 600KHz offset, and 76.3MHz/V tuning sensitivity. The circuits are simulated with Agilent EEsof EDA-RFIC Designer in 0.35 μm TSMC technology, and the results show 2.7 dB overall noise figure, —1.2 dBm IIP3, and 148.17 mW power consumption.

ABSTRACT (in Chinese) Ⅰ
ABSTRACT (in English) Ⅱ
ACKNOWLEDGEMENT Ⅲ
CONTENTS Ⅳ
LIST OF FIGURES Ⅶ
LIST OF TABLES Ⅹ
1 INTRODUCTION 1
1.1 Motivation 1
1.2 Organization 2
2 ARCHITECTURE OF THE RECEIVER FRONT-END 3
2.1 Heterodyne or IF Receiver 3
2.1.1 Single-Stage Receiver 3
2.1.2 Multi-Stage Receiver 4
2.2 Problem of the Heterodyne Architecture 5
2.3.1 Problem of Image 5
2.3.2 Problem of HalfIF 6
2.3 Heterodyne Fundamental 6
2.4.1 Noise Figure 6
2.4.2 Third-Order Intercept 8
2.4.3 Spurious-Free Dynamic Range 8
3 COMPONENTS OF THE HETERODYNE RECEIVERS 10
3.1 Inductor 10
3.11 Planar Inductor 10
3.12 Inductor model 11
3.2 MOSFET 12
3.2.1 Thermal Noise 13
3.2.2 FlickerNoise 13
3.2.3 Design of RF MOSFET 14
3.3 LNA 14
3.3.1 The Input Impedance 14
3.3.2 Noise Performance 16
3.4 Single-Ended And Differential LNA 16
3.4.1 Single-Ended LNA 16
3.4.2 Differential LNA 17
3.5 Mixer 18
3.5.1 Introduction 18
3.5.2 Passive and Active Mixer 18
3.5.3 Fundamental of Mixer 19
3.5.4 Conversion Gain 21
3.5.5 Linearity 21
3.5.6 Isolation 22
3.5.7 Single-Balanced Mixer 22
3.5.8 Double-Balanced Mixer 24
3.6 Voltage-Controlled Oscillator 27
3.6.1 Introduction 27
3.6.2 Phase Noise 27
3.6.3 Phase Noise in Receiver 29
3.6.4 Varactor 32
3.6.5 Negative Resistance Oscillator 32
4 HETERODYNE RECEIVER IMPLEMENTATION 37
4.1 Overview 37
4.2 Single-Ended LNA 37
4.2.1 LNA Implementation 37
4.2.2 Simulation Results 39
4.3 Double-Balanced Mixer 41
4.3.1 Mixer Implementation 41
4.3.2 Simulation Results 42
4.3.2.1 The First Mixer 42
4.3.2.2 The Second Mixer 46
4.4 Voltage-Controlled Oscillator 48
4.4.1 VCO Implement 48
4.4.2 Simulation Results 49
4.5 The Overall 51
5 CONCLUSION 53
REFERENCES 54

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