臺灣博碩士論文加值系統

在現今網路盛行的時代，使用者對於影音多媒體效果的要求，使得在網路上傳送影音資料變得非常頻繁，其中又以影像資料最佔頻寬，這也使得使用者因網路頻寬的不足，而增加了等待的時間，通常為了降低影像資料的傳輸量，在數位影像的傳輸與儲存的應用上，低位元率（low bit rate）壓縮方法是必要的。目前已有多個影像編碼技術被提出，其中又以小波轉換（wavelet transform）提供了最佳的影像編碼應用。在小波轉換的基礎下，EZW （Embedded Zerotree Wavelet）與SPIHT（Set Partitioning In Hierarchical Trees）這兩種演算法，被廣泛應用在影像壓縮上，且嵌入式小波影像壓縮編碼都具備漸進式傳輸，精確性控制編碼長度及容錯等優點。另外，嵌入式影像處理可應用於即時（real-time）壓縮系統，但若要做為即時的壓縮高解析的靜態或動態影像，則必須使用數位信號處理器（DSP）或超大型積體電路（VLSI）來實現它。所以本論文將深入探討這兩種演算法之特性，著重於影像之EZW編碼演算法硬體架構推導與設計，並將EZW演算法加以改良，使之適用於實際超大型積體電路硬體實現。最後經由相關的電腦輔助設計軟體的協助下完成電路設計及功能模擬驗證。

In the network era, video/audio transmission is frequent due to the demand of multimedia users. Because video/image data takes most of bandwidth, which is usually deficient in such an application, users have to wait for a longer period to access the image data through network. To lower the amount of transmitted image data, low-bit-rate compression is then necessary in image transmission and storage. There are several techniques of image coding being mentioned so far, and among them, the wavelet transform offers the best way in image coding. On the basis of wavelet transform, the EZW (Embedded Zerotree Wavelet) and SPIHT (Set Partitioning In Hierarchical Trees) are widely used in the image compression. The embedded compression technique provides several superior properties like progressive transmission, coding-length-control, and fault tolerance such that it can be applied for real-time compression systems. In conjunction with the DSP (digital signal processor) or ASIC (application specific integrated circuit) realization, real-time compression can be further achieved for high-resolution moving or still images. This thesis is to explore the characteristics of both EZW and SPIHT and focuses on the design of EZW. In the meanwhile, we modify the existing EZW so as to fit in the VLSI implementation. Finally, this thesis concludes with the demonstration of the resulting functional verification and performance evaluation.

中文摘要---------------------------------------------i
英文摘要---------------------------------------------ii
致謝---------------------------------------------iii
目錄---------------------------------------------iv
圖目錄---------------------------------------------vi
表目錄---------------------------------------------viii
一、序論----------------------------------------------1
1.1 研究動機--------------------------------------1
1.2 研究目標--------------------------------------2
1.3 論文摘要--------------------------------------2
二、漸進式編碼演算法----------------------------------3
2.1 簡介------------------------------------------3
2.2 EZW演算法-------------------------------------4
2.3 EZW演算法範例---------------------------------10
2.4 EZW演算法模擬---------------------------------13
2.5 SPIHT演算法-----------------------------------15
2.6 SPIHT演算法範例-------------------------------20
2.7 SPIHT演算法模擬-------------------------------23
三、漸進式編碼硬體架構之相關研究----------------------24
3.1 簡介------------------------------------------24
3.2 EZW硬體架構相關研究---------------------------24
3.3 SPIHT硬體架構相關研究-------------------------34
四、嵌入式零樹編碼硬體架構設計------------------------37
4.1 簡介------------------------------------------37
4.2 深度搜尋與廣度搜尋----------------------------38
4.3 硬體版本之EZW演算法模擬-----------------------41
4.4 EZW編碼器架構設計-----------------------------42
4.5 記憶體空間需求--------------------------------49
五、硬體實現與結果模擬--------------------------------50
5.1 簡介------------------------------------------50
5.2 設計流程--------------------------------------50
5.3 EZW編碼器硬體模擬環境與模擬結果---------------53
5.4 硬體架構閘數統計------------------------------54
5.5 EZW編碼系統硬體架構比較-----------------------55
5.6 EZW編碼實例-----------------------------------56
六、結論與未來發展------------------------------------59
參考文獻----------------------------------------------60
自傳--------------------------------------------------65

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