由於繞線的執行處於整個實體設計過程的後段，假如繞線的執行成效不佳，那麼我們先前所完成的步驟將不斷地反覆被執行，來改善繞線不佳的窘境。在這個反覆改善設計的過程當中，產品便會失去市場的先機。為了增加繞線的成功機率，我們應該及早進行繞線的規劃。在這篇論文當中，我們發展了一個簡單的置放後可繞性分析器。這個方法是基於計算每一個detailed routing graph vertex上的垂直方向繞線密度與水平方向繞線密度，其中當然也會考慮了繞線前障礙物所造成的影響，這些障礙物包括了邏輯元件的接腳與置放前之繞線。我們利用可繞性分析器來調整的晶片面積與繞線層數。根據實驗結果，我們觀察到我們的方法可以正確地預估最小晶片面積的繞線層數。然而截至目前為止，我們還是無法正確地調整出晶片面積使整個晶片得以完成繞線。

Because routing is performed at the very end of the design process, if the routing of a design is badly performed, the design tasks previously done before routing may be iterated again to solve the routing problem. This often incurs a delay for time-to-market. In order to increase the probability of having a successful routing, routing planning should be performed early. This thesis develops a simple methodology to perform post placement routability analysis. The methodology is based on the vertical and horizontal wiring densities calculated for each of the detailed routing graph vertexes by taking into account the blockages formed by cell pins, prerouted wires, etc. The routability analyzer is used to tune chip area and the number of routing layers. The experimental results show that it can accurately estimate the number of routing layers for a chip but can not accurately predict the chip area. It is yet to find out an effective method to tune chip area.

Chapter 1. Introduction
1.1 Background
1.2 Scope of the Work
1.3 Thesis Organization
Chapter 2. Related Work
2.1 Routability Analysis Based on Circuit Netlist
2.2 Routability Analysis During or Post Placement
2.3 Routability Analysis in Other Applications
Chapter 3. A Post Placement Routability Analyzer
3.1 Preliminaries
3.2 Implementation
3.2.1 Definitions
3.2.2 Handling Pre-routing Obstacles
3.2.3 Wiring Length Estimation
3.2.4 Layer Estimation
3.2.5 Track Insertion
Chapter 4. Experimental Results
Chapter 5. Conclusions and Future Work

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