臺灣博碩士論文加值系統

CD(Clock-Delayed) domino logic circuits擁有比傳統式的的Domino Logic Circuit 更快的速度與更小的面積；非常適合使用於高性能電路的設計，在本論文中針對CD domino logic circuits 特性的提升作為研究，在提升速度與降低功率損耗兩方面同時進行探討時，引入我的指導教授所提出新的CD Domino Logic電路－Pseudo Footless Domino Logic circuit，本論文中針對Pseudo Footless Domino Logic circuit如何應用在一般電路中提出三種變形的電路，並證明能比相同的Domino Logic circuit擁有更優良的特性。而在Clock訊號方面：針對CD Domino Logic Gate Clock訊號之Delay Element的設計亦提出self-tracking的機制，防止因變化因素(如:製程、電壓、與溫度變動…)變動而導致輸出函數錯誤，並且從data與clock的timing關係來改善delay element設計的方法來達到加快整體電路的速度目的。並將所提出的三種變形的Pseudo footless domino logic電路與使用self-tracking方法所設計的delay element，搭配分析timing時所得到可加快電路速度的方法，將三種方法一起配合，並實際應用在一個32-bit CLA上，並與其他種類的動態電路與Static CMOS電路所組成的CLA一起來比較，此CLA電路模擬是採用0.25um CMOS TSMC的製程參數，而模擬時亦考慮因製程變動所會產生的結果，而引用新的CD Domino Logic Circuit配合所提出的self-tracking的技巧，可使新的CD Domino Logic在製程變動之下輸出依舊能維持正確的值，在pre-simulation正確的輸出下測得由新的CD Domino Logic Circuits所組成的CLA，其worst-case運算結果時間為 0.98 ns，比由DR Domino Logic Circuits所組成相同架構的CLA快1.43倍，比舊型的CD Domino Logic Circuits所組成的CLA快1.63倍，比Static CMOS所組成的CLA快2.04倍，而在功率損耗上亦不會比Static Logic所組成的CLA大很多。在post-simulation時，由於加入wire-loading測得新的CD Domino Logic其post-sim結果為1.1ns，舊型的CD Domino Logic Circuits所組成的CLA為1.82ns，DR Domino Logic Circuits其為1.66ns，所以能證明新型的CD Domino Logic Circuits比其他種類的Domino Logic更適合使用在邏輯的合成與晶片實現上。

CD(Clock-Delayed) domino logic circuits design offers higher speed and smaller area than conventional domino logic circuit; it is very popular in the high-performance circuits design. This paper presents new CD domino logic circuit that is derived from Pseudo Footless (PF) domino logic. The pseudo footless domino logic circuit can simultaneously to improve the performance and reduce power dissipation. Moreover, the Self-Tracking technique is also presented for the design of delay element. When the fabrication processes variations, voltage variations, temperature variations, the self-tracking technique guarantees output functional correctness. The methodology with pseudo footless domino logic is demonstrated by the design of a 32-bit CLA using TSMC 0.25-um process. Pre-layout simulations of the adder show a worst-case delay time of 0.98 ns. The PF domino logic adder circuit can operate 1.43times faster than the Footless domino adder, 1.63times CD domino adder, and 2.04times than the static CMOS adder if the same CLA architecture is adopted. The power consumption of the PF Domino adder is slightly higher than that of the static one. Post-layout simulation of the PF Domino CLA, which includes the wire loading, shows a worst-case delay time of 1.1ns. In contrast, Conventional CD Domino adder spends 1.82ns; DR Domino adder spends 1.66ns. Therefore, The PF Domino Logic provides better performance in logic synthesis and circuit implement.

I. 簡 介 3
II. 各種Domino Logic Circuits介紹與分析 5
2-1.Conventional Domino Logic Circuits 5
2-2. Delayed Reset Domino Logic Circuits 8
2-2-1. DR (Asynchronous) Domino Logic Circuits 11
2-2-2. DR (Synchronous) Domino Logic Circuits 15
2-2-3. DR Domino Logic Circuits Constrain 17
2-3. CD Domino Logic Circuits 18
III. 比較Conventional、DR 、CD Domino Logic Circuits 24
IV. Self-Timed Pseudo Footless CD Domino Logic 28
4-1. 提升 CD Domino Logic Gate速度的方法 29
4-2. PDN Sizing的方法 32
4-3. 考量將Pseudo Footless Domino Logic使用於電路的設計方法 33
4-4. 比較新的CD Domino Logic與其他電路的特性 36
V. Self-Timed Delay Element的設計 37
5-1. 設計Delay Element在時脈上的限制 37
5-2. 變化因素變動時影響Delay Element的Timing考量 40
5-3. 考慮變動因素下Delay element的設計 42
VI. 新的CD Domino Logic應用在32-bit CLA電路 46
6-1. 動態與靜態電路邏輯閘動作時間計算方法 47
6-2. 評估動態電路的AND Gate與OR Gate的特性 48
6-3. 32-bit CLA電路架構 49
6-4. 32 bit CLA pre-simulation的結果： 52
6-5. 32 bit CLA post-simulation的結果： 54
6-6. 32 bit CLA 測試考量： 58
VII. Conclusion 60
VIII. 未來研究方向 62
Reference paper 63

[1] Hofstee, H.P.; Sang H. Dhong; Meltzer, D.; Nowka, K.J.; Silberman, J.A.; Burns, J.I.; Posluszny, S.D.; Takahashi, O., “Designing for a gigahertz [guTS integer processor],” IEEE Micro , Volume: 18 Issue: 3 , May-June 1998, Page(s): 66 -74
[2] Aipperspach, A.G.; Allen, D.H.; Cox, D.T.; Phan, N.V.; Storino, S.N., “A 0.2-/spl mu/m, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects, ” Journal of Solid-State Circuits, Volume: 34 Issue: 11 , Nov. 1999 Page(s): 1430 —1435
[3] Sung-Mo Kang, “CMOS Digital Integrated Circuits, “2nd Edition
[4] Jinn-Shyan Wang, “VLSI電路設計, “
[5] Neil H. E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI Design, “
[6] Silberman, J..etc., “A 1.0-GHz single-issue 64-bit powerPC integer processor, “ IEEE Journal of Solid-State Circuits, Nov. 1998, pp: 1600 —1608
[7] Dharchoudhury, A.; Blaauw, D.; Norton, J.; Pullela, S.; Dunning, J., “Transistor-level sizing and timing verification of domino circuits in the Power PC/sup TM/ microprocessor,” Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on , 1997 Page(s): 143 -148
[8] Heald, R. etc., “A third-generation SPARC V9 64-b microprocessor, “ IEEE Journal of Solid-State Circuits, , Volume:. 2000 ,Page(s): 1526 —1538
[9] Gin Yee,“Dynamic Logic and Synthesis Using Clock-Delay Domino,“ The doctoral dissertation 1999
[10] Gin Yee; Sechen, C, “Dynamic logic synthesis,” Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997 , 1997 ,Page(s): 345 -348
[11] Gin Yee; Sechen, C, “Clock-delayed domino for dynamic circuit design,” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , Volume: 8 Issue: 4 , Aug. 2000 ,Page(s): 425 -430
[12] Wei-Han Lien; Burleson, “Wave-domino logic: theory and applications, ” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on , Volume: 42 Issue: 2 , Feb. 1995 ,Page(s): 78 -91
[13] Jinn-Shyan Wang; Ching-Rong Chang; Chingwei Yeh, “Analysis and design of high-speed and low-power CMOS PLAs,” Solid-State Circuits, IEEE Journal of , Volume: 36 Issue: 8 , Aug. 2001 ,Page(s): 1250 -1262
[14] Harris, D.; Horowitz, M.A, “Skew-tolerant domino circuits, ” Journal of Solid-State Circuits, IEEE, Volume: 32 Issue: 11 , Nov. 1997 ,Page(s): 1702 -1711