本論文為其改善傳統階層式電路設計的瓶頸，以一個可分割電路模型，提出了新的解決方法。其中，並考慮MOS製程的臨界電壓參數變動，運用元件相互間的相關特性，模擬元件不匹配效應對整體電路效能的影響。

This thesis gives a method to have a circuit be separable that the hierarchical design was confronted. It is hoped that a circuit under simulation can be separated into several parts arbitrarily. The separable circuit model is analyzed with consideration of the correlation between the devices for mismatch effects that influence the performance of the simulated circuit. By considering the variation of transistor threshold voltages, it has been shown that the simulated input offset of an operational amplifier is valid of using separable model.

摘要 ……………………………………………………………………Ⅰ
Abstract ………………………………………………………………Ⅱ
誌 謝 辭 ………………………………………………………………Ⅲ
目錄 ……………………………………………………………………Ⅳ
圖目錄 …………………………………………………………………Ⅵ
表目錄 …………………………………………………………………Ⅷ
第一章 簡介 …………………………………………………………1
第二章 統計與階層式設計的介紹…………………………………..3
2.1 階層式設計方法(hierarchical) …………………………………3
2.2 常態分佈 (Normal Distribution) ……………………………4
2.3 相關係數 (Correlation Coefficient) ……………………………..6
第三章 製程變動與元件特性………………………………………..8
3.1 IC製程上的擾動……………………………………………8.
3.2 MOS元件結構及操作原理…………………………………..9
第四章 運算放大器………………………………………………….14
4.1運算放大器的特性介紹……………………………………..14
4.2輸入偏移電壓……………………………………………….15
第五章 相關係數對電路性能的影響分析…………………………..18
5.1元件參數分析…………………………………………………18
5.2電路架構………………………………………………………21
5.3實驗步驟與結果………………………………………………23
第六章 相關性運用在階層式的模擬………………………………..30
6.1實驗流程……………………………………………………..30
6.2實驗結果……………………………………………………..34
第七章 結論 ……………………………….………………………..40
參考文獻 ……………………………………………………………….41

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