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研究生:羅珮文
研究生(外文):Pei-wen Luo
論文名稱:針對可分割電路模型容忍分析之新穎規劃
論文名稱(外文):A Novel Scheme for Tolerance Analysis with a Separable Circuit Model
指導教授:陳竹一
指導教授(外文):Jwu E Chen
學位類別:碩士
校院名稱:中華大學
系所名稱:電機工程學系碩士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:43
中文關鍵詞:可分割電路相關性不匹配特性
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本論文為其改善傳統階層式電路設計的瓶頸,以一個可分割電路模型,提出了新的解決方法。其中,並考慮MOS製程的臨界電壓參數變動,運用元件相互間的相關特性,模擬元件不匹配效應對整體電路效能的影響。

This thesis gives a method to have a circuit be separable that the hierarchical design was confronted. It is hoped that a circuit under simulation can be separated into several parts arbitrarily. The separable circuit model is analyzed with consideration of the correlation between the devices for mismatch effects that influence the performance of the simulated circuit. By considering the variation of transistor threshold voltages, it has been shown that the simulated input offset of an operational amplifier is valid of using separable model.

摘要 ……………………………………………………………………Ⅰ
Abstract ………………………………………………………………Ⅱ
誌 謝 辭 ………………………………………………………………Ⅲ
目錄 ……………………………………………………………………Ⅳ
圖目錄 …………………………………………………………………Ⅵ
表目錄 …………………………………………………………………Ⅷ
第一章 簡介 …………………………………………………………1
第二章 統計與階層式設計的介紹…………………………………..3
2.1 階層式設計方法(hierarchical) …………………………………3
2.2 常態分佈 (Normal Distribution) ……………………………4
2.3 相關係數 (Correlation Coefficient) ……………………………..6
第三章 製程變動與元件特性………………………………………..8
3.1 IC製程上的擾動……………………………………………8.
3.2 MOS元件結構及操作原理…………………………………..9
第四章 運算放大器………………………………………………….14
4.1運算放大器的特性介紹……………………………………..14
4.2輸入偏移電壓……………………………………………….15
第五章 相關係數對電路性能的影響分析…………………………..18
5.1元件參數分析…………………………………………………18
5.2電路架構………………………………………………………21
5.3實驗步驟與結果………………………………………………23
第六章 相關性運用在階層式的模擬………………………………..30
6.1實驗流程……………………………………………………..30
6.2實驗結果……………………………………………………..34
第七章 結論 ……………………………….………………………..40
參考文獻 ……………………………………………………………….41

[1] Dr. An-Chang, Dr. Sang Wang著, 王文彥譯, “Hierarchical 處理方法在Post-Layout SOC模擬驗證中的重要性,” IC design, May, 2001, pp. 117-120
[2] U. Schaper, “Precise characterization of long-distance mismatch of CMOS devices,” IEEE trans. on semiconductor manufacturing, vol. 14, No. 4, November 2001, pp. 311-317.
[3] X. Zhou, K. Y. Lim, and D.Lim, “A general approach to compact threshold voltage formulation based on 2-D numerical simulation and experimental correlation for deep-submicron VLSI technology development,” IEEE trans. on electron devices, vol. 47, No. 1, January 2000, pp.214-221.
[4] Tuna B. Tarim and Mohammed Ismail, “Enhanced analog “yields” cost-effective systems-on-chip,” IEEE trans. circuits &devices, 1999, pp. 12-22.
[5] M. Conti, P. Crippa, S. Orcioni, and C. Turchetti, “Parametric yield formulation of MOS IC’s affected by mismatch effect,” IEEE Trans. Circuit and Syst., vol. 18, no. 5, May 1999, pp.582-596.
[6] M. J.M. Pelgrom, H. P. Tuinhout, and M..Vertregt, “Transistor matching in analog CMOS applications,” in IEDM Tech. Dig., 1998, pp. 915-918.
[7] T. Smedes and P.G.A. Emonts, “Statistical modeling and circuit simulation for design for manufacturing,” in IEDM Tech. Dig., 1998, pp. 763-766.
[8] C. Michael and M. Ismail, “Statistical modeling of device mismatch for analog MOS intrgrated circuits,” IEEE journal of solid-state circuits, vol. 27, No. 2, February 1992, pp.154-166.
[9] W. Maly, “Computer-Aided design for VLSI circuit manufacturability,” proceedings of the IEEE, vol. 78, No. 2, February 1990, pp.356-392.
[10] W. Maly, S. W. Director, and A, J, Strojwas, VLSI Design for Manufacturing:Yield Enhancement, Kluwer Academic Publishers, 1990.
[11] Marcel J. M, Pelgrom, “Matching properties of MOS transistors,” IEEE journal of solid-state circuits, vol. 24, No. 5, October 1989, pp. 1433-1440.
[12] P. E. ALLEN and D. R. HOLBERG, CMOS Analog Circuit Design, Harcourt Brace Jovanovich College Publishers, 1987.
[13] Paul R. Gray, R. G. Meyer原著, 胡振國編譯, “類比積體電路分析與設計”, 1995 全華出版社。

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