|
[1] Cong, J., Sung Kyu Lim, “Performance Driven Multiway Partitioning,” Asia and South Pacific Design Automation Conference, pp. 441-446, 2000.[2] Minami, J., Koide, T., Wakabayashi, S., “A circuit partitioning algorithm under path delay constraints,” IEEE Asia-Pacific Conference on Circuits and Systems, pp. 113-116, 1998. [3] Ababei, C.; Kia Bazargan, “Statistical timing driven partitioning for VLSI circuits,” Proceedings of Design Automation and Test in Europe Conference and Exhibition, pp. 1109 -1109, 2002[4] Chau-Shen Chen; Ting Ting Hwang; Liu, C.L., “Architecture driven circuit partitioning,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 9 Issue:2, pp. 383-389, April 2001.[5] Wen-Jong Fang; Wu, A.C.-H., “A hierarchical functional structuring and partitioning approach for multiple-FPGA implementations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.16 Issue:10,pp.1188-1195, Oct. 1997.[6] Wen-Jong Fang; Wu, A.C.-H., “Multi-way FPGA Partitioning By Fully Exploiting Design Hierarchy,“ Proceedings of Design Automation Conference, pp. 518 -521, 1997.
|