臺灣博碩士論文加值系統

中文摘要
近年來非揮發性記憶體在半導體記憶元件的發展與研究上，其所扮演的角色是愈來愈重要。而隨著可攜式產品，如筆記型電腦、數位相機等的普及，非揮發性記憶體的技術也是逐年在進步。從最早的唯讀記憶體(Read-Only-Memory，ROM)、可程式唯讀記憶體(Programmable-Read-Only-Memory，PROM)，到可抹除程式化唯讀記憶體(Erasable- Programmable-Read-Only-Memory)、電性可抹除程化唯讀記憶體(Electrically Erasable Programmable Read Only Memory，EEPROM)，以至目前最熱門的快閃記憶體(Flash Memory)，揮發性記憶體在其結構上亦隨之改變。然而，近來矽-氧化矽-氮化矽-氧化矽-矽(Silicon-Oxide-Nitride-Oxide-Silicon，SONOS)記憶體元件受到相當大的注意，主要是其在CMOS製程上有著相當高的整合性，可以大大地降低生產成本。
本論文是以SONOS記憶元件為研究主題，且並提出具有矽離子佈值之SONOS記憶元件來提昇其寫入與抹除的效率。本論文首先就SONOS記憶體元件的操作原理做介紹，如利用通道熱電子做為寫入機制和利用熱電洞的注入做為抹除機制。在模擬方面，使用了TSUPREM4及MEDICI對SONOS元件做製程及電性上模擬。從模擬中可以發現使用通道熱電子注入來做寫入是具有區域性儲存的特性(localized trapping)，這在做多位元記憶上有相當的助益。並利用模擬在順向讀出(forward read)和反向讀出(reverse read)的差異上做比較與探討。實驗方面，提出了具有矽離子佈值的SONOS元件與未做矽離子佈值的SONOS元件做比較，從實驗結果中可以發現矽離子佈值SONOS元件具有較大的寫入/抹除效率、較快的寫入/抹除時間和較大的寫入/抹除邏輯位差。因此SONOS元件經由離子佈值後更適合做為記憶元件。

Abstract
Non-Volatile Memory (NVM) has been developed and improved in past years, and recently it has been received much attention in mobile or portable applications, such as mobile phones, smart cards and digital camera. First, the history of the Non-Volatile Memory (NVM) and the concept of the NVM are introduced. And the typical NVMs, such as EPROM, EEPROM, flash memory are also introduced. Nowadays, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) becomes the most popular charge-trapping device because of its complete compatibility with existing advanced CMOS technology. Fowler-Nordheim (FN) tunneling and Channel-Hot-Electron Injection (CHEI) are usually used to program the SONOS cell as a single bit cell and a two-bit cell respectively. And the hot hole enhanced injection (HHEI) are used to erase the two-bit cell. And these mechanisms are introduced in chapter two.
In this thesis, Si-implanted SONOS cell is proposed to improve the data retention of the SONOS cell. TSUPREM4 and MEDICI are used to simulate the cell. A SONOS cell without Si-implanted is prepared to compared the Si-implanted one. Both of experiment and simulation show that the Si-implanted SONOS cell has the better program/erase efficiency and broader program/erase window.

Contents
中文摘要
Abstract
Acknowledgments
Contents
Figure captions
Table captions
章節摘要
第一章非揮發性記憶體之回顧
第二章SONOS記憶元件之物理原理
第三章矽離子佈值之SONOS元件模擬
第四章矽離子佈值SONOS元件之評估
第五章總結與未來工作
An Overview of Non-Volatile Memory
1-1 Introduction of Non Volatile Memory
1-2 Floating Gate Device
1-2-1. Stacked Gate Memory Devices
1-2-2. Split Gate Memory Devices
1-3 Metal-Insulator-SiO2 —Si (MIOS) Device
1-4 Development Trends
1-5 Organizations
Physical Aspects of SONOS Memroy Cell
2-1 Introduction
2-2 The Mechanism of Hot Carrier Effect (HCE)
2-3 Hot Carrier Effect (HCE) for the SONOS
2- 3-1 Programming
2- 3-2 Erasing
2-4 The “Read” operation of SONOS
2-4-1 “Forward Read”
2-4-2 “Reverse Read”
2-5 The Data retention loss in the localized storage SONOS
2-6 Conclusions
The Simulation of Si-implanted SONOS
3-1 Introduction
3-2 The Process Flow of the Si-Implanted SONOS Device
3-3 The Simulation of Si-Implanted SONOS Memory
3-3-1 The Simulation of Si-implantation
3-3-2 The TSUPREM4 Simulation of Si-implanted SONOS
3-3-3 The MEDICI Simulation of Si-implanted SONOS
3-4 Results and Discussions
3-5 Conclusions
Evaluation of Si-implanted SONOS
4-1Device Fabrication
4-2 Device Characterization
4-2-1 Configuration of Measurement System
4-2-2 Threshold Voltage (Vth) and Transient Measurement
4-3 Results and Discussions
4-4 Conclusions
Conclusions and Future Works
5-1 Conclusions
5-2 Future Works

Reference:[1]Paolo Cappelletti, Carla Golla, Piero Olivo, Enrico Zanoni, “Flash Memory”[2]沈士傑，徐清祥，”淺談怏閃式記憶體之發展”，電子月刊第二第九期，1996年九月號.[3]S. M. Sze, “ Physics of Semiconductor Devices”, 2nd Edition[4]C. Y. Chang and S. M. Sze, “ULSI DEVICES”[5]A. T. Wu, T. Y. Chan, P. K. Ko, and C. Hu, “A novel high-speed, 5V programming EPROM structure with source-side-injection”, IEDM Tech. Dig, 1986, pp.584-587.[6]Marvin H. White, Dennis A. Adams, and Jiankang Bu, “On the Go with SONOS”, IEEE Circuits and Devices, July 2000[7]Boaz Eitan, Paolo Paven, Ilan Bloom, Efrain Aloni, Aviv Frommer, and David Finzi, “NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell”[8]STANLEY WOLF, “Silicon Processing For The VLSI ERA volume3: The Submicron MOSFET”[9]K. Hasnat, C. F. Yeap, S. Jallepalli, W. K. Shih, S. A. Hareland, V. M. Agostinelli, A. F. Tasch, and C. M. Maziar, “A Pseudo-Lucky electron model for simulation of electron fate current in submicron N-MOSFET’s”, IEEE Tran. Electron devices, vol.43, no.8, August 1996, p.1264[10]T. Y. Chan, K. K. Young, C. Hu, “ A True Single Transistor Oxide-Nitride-Oxide EEPROM,” IEEE Electron Device Letters, EDL-8, No3, March 1987, pp. 93~95[11]Boaz Eitan, Paolo Paven, Ilan Bloom, Efrain Aloni, Aviv Frommer, and David Finzi, “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?”[12]Cheng T. Wang, “Hot Carrier Design Considerations for MOS Devices and Circuits”[13]W. S. Feng, T. Y. Chan, and C. Hu, “MOSFET drain breakdown voltage,” IEEE Electron Device Lett., vol. EDL-6, p. 449, July 1986[14]M.S. Liang and T. C. Lee, “A hot-hole erasable memory cell,” IEEE Electron Device Lett., vol. EDL-7, p. 463 Aug. 1986[15]U.S. Patent 6,011,725 “Two Bit Non-Volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping”[16]W. J. Tsai, N. K. Zous, C. J. Liu, C.C. Liu, C. H. Chen, Tahui Wang, Sam Pan And Chih-Yuan Lu, “Data Retention Behavior of a SONOS Type Two-Bit Storage Flash Memory Cell[17]Yakov Roizin, Micha Gutman, Efraim Aloni, Victor Kairys, Pavel Zisman, “Retention Characteristics of microFLASH Memory (Activation Energy of Traps in the ONO stack)[18]W. J. Tsai, N. K. Zous, C. J. Liu, C.C. Liu, C. H. Chen, Tahui Wang, Sam Pan And Chih-Yuan Lu, “ Cause of Data Retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell’ 40th Annual International Reliability Physics Symposium, 2002[19]S. ManZini and A. Modelli, “Tunneling Discharge of Trapped Holes in Silicon Dioxide”, in Insulation Films on Semiconductors, J. F. Verwij and Wolters, Eds. Amsterdam, The Netherlands; Elsevier, p. 112, 1983[20]DIETER K. SCHRODER, “ Semiconductor Material and Device Characterization”[21]Eli Lusky, Yosi Shacham-Diamand, Ilan Bloom, Boaz Eitan, “Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROMTM Device”, IEEE Electron Device Letters, vol. 22, No11, November 2001[22]T. Ohzone, T. Matsuda, and T. Hori, “Erase/Write Cycle Tests of n-MOSFET’s with Si-implanted Gate-SiO2”, IEEE Trans. On Electron Devices, Vol.43, No.9, pp.1374, 1996