臺灣博碩士論文加值系統

摘要
印刷電路板的製造方式一般可分為減成法 (Subtractive Process)與加成法 (Additive Process) 兩種。減成法是將已經壓合有銅箔的聚亞胺樹脂 P I (Polyimide) 基板或是玻璃纖維基板上去除非線路部分的銅箔，留下的部分即為所需要的金屬線路；加成法則是在非導電性的基板上直接析鍍所需要的金屬線路。由於使用減成法在溫度控制、蝕刻液配方和蝕刻噴嘴角度控制有少許的誤差下會有側蝕與殘銅的問題，使得電路板在細線化過程中遇到些許的瓶頸。所以本實驗想利用加成法電路板製程，試驗是否能直接析鍍所需要的特定金屬線路，並且嘗試加以微影縮小。兩種方法在印刷電路板的製造過程中各有優點和缺點，但是本實驗想利用加成法所具有的優點：(1)製造流程簡化 (2)適合大量生產 (3)銅鍍層厚度均勻，不會有側蝕問題 (4)適合製造細線路。
本實驗的構想是不利用到化學蝕刻、不使用抽真空的儀器設備來做濺鍍或蒸鍍的工作、在非無塵室的環境下進行電路析鍍，以便節省高額的儀器設備成本。利用較低廉的無電鍍法結合電腦繪圖設計在各種材質的基板上析鍍不同的金屬 (如：銅、鎳)。但是在加入活化劑 (Activator) (PdCl2)的過程中，利用到印表機與其他物品的輔助，直接把氯化鈀 (PdCl2)印在想要繪製線路的基板上，並且控制線路圖形的形狀與大小。最後再將所析出的金屬做一些基礎的電性與物性測量，得到在室溫環境 (20∼25℃) 析鍍鎳金屬線路的電阻率 ρ＝1.2518×10-4 Ω-m ； 銅金屬線路的電阻率ρ＝4.6330×10-7 Ω-m 。
在加溫環境 (45∼50℃) 析鍍鎳金屬線路的電阻率 ρ＝0.77696×10-4 Ω-m ； 銅金屬線路的電阻率ρ＝2.7593×10-7 Ω-m 。

Abstract
Generally, there are two ways for electric circuit printing: Subtractive Process and Additive Process. The Subtractive Process is to remove copper on the non-circuit portion of copper imprinted PI (Polyimide) baseboard or glass fiber baseboard and the remaining will be the needed metal circuits. The additive process is, on the other hand, directly plating the needed metal circuit onto the non-conductive baseboard. Under the Subtractive Process, minor errors in temperature control, recipe of etchant, and the angle control of etching nozzle can all cause problems like laternal etching and copper residue, which in turn contributed to bottlenecks in the hairlining processes for the circuit board production. Therefore, we tried to incorporate the additive process for use in the circuit board production processes in the experiment, test if feasible to directly plate the needed specific metal circuits and attempt to turn it into microfiche. There are both pros and cons for those two methods in the circuit boards printing process, however, in this experiment, we would like to employ all the advantages from the additive process: (1) Simplified production process, (2) Good for mass production, (3) Even thickness throughout the plated copper layer and without laternal etching, (4) Ideal for producing hairline circuits.
The envision of this experiment is to save on large amount of instrumentation costs by leaving out chemical etching, Cathodic Sputtering or Direct Vacuum Deposition with vacuum pumping instruments, and electroplating under the clean room environment. We adopted less expensive electroless plating method in combination with computer drawing design to plate different kinds of metal onto a variety of baseboards (such as copper and nickel). Nevertheless, we also utilized assistances from printer and other devices during the process for adding the activator─PdCl2, we imprinted the PdCl2 directly onto the baseboard intended for circuit drawing and controlled the shapes and sizes of the drawing itself. Lastly, we then performed some basic electrical and physical measuring on those educed metals, we had that under the room temperature (20oC~25oC), the resistivity for the nickel-plated circuit was s = 1.2518 x 10-4W-m, the resistivity for copper plated circuit was s = 4.6330 x 10-7W-m. Under an increased temperature environment (40oC~45oC), the resistivity for the nickel-plated circuit was s = 0.77696 x 10-4W-m, the resistivity for copper plated circuit was s = 2.7593 x 10-7W-m.

總目錄
封面………………………………………………………………………1
中文摘要…………………………………………………………………2
英文摘要…………………………………………………………………4
誌謝………………………………………………………………………7
總目錄……………………………………………………………………8
圖目錄…………………………………………………………………..10
表目錄…………………………………………………………………..12
第一章 緒論………………………………………………..…………14
1-1前言……………………………………………….………………...14
1-2文獻回顧……………………………………………………………15
1-3研究目的……………………………………………………………16
第二章 原理…………………………………………………………..17
2-1無電鍍之原理…………………………………………..…………..17
2-2無電鍍銅……………………………………………………………18
2-3無電鍍鎳……………………………………………………………19
2-4無電鍍操作變數……………………………………………………20
2-5生產流程圖…………………………………………………………23
第三章 實驗步驟……………………………………….…………….28
3-1鍍液的調配…………………………………….…………………...28
3-2基底的表面清潔處理………………………………………………30
3-3實驗步驟……………………………………………………………31
3-4實驗步驟流程圖……………………………………………………34
第四章 結果與討論…………………………………………………..38
4-1室溫環境下析鍍銅金屬線路…………………………………..…..38
4-2室溫環境下析鍍鎳金屬線路…………………………………..…..42
4-3加溫環境下析鍍銅金屬線路……………………………………....47
4-4加溫環境下析鍍鎳金屬線路………………………………………51
4-5改變配方環境下析鍍銅金屬線路………………………………....55
4-6改變配方環境下析鍍鎳金屬線路……………………………...….59
4-7析鍍結果與討論……………………………………………….…...63
4-8析鍍金屬在SEM下的結構………………...……..…………………68
第五章 結論與建議…………………………………………………..70
第六章 參考文獻………………………………………………..……73

第六章 參考文獻【1】A.Brenner and G.Riddell, Proceeding Amer. Electrolater Soc. 33 pp.16(1946); 34 pp.156(1947)【2】莊萬發“無電解鍍金-化學鍍金技術”,復漢出版社(2001)【3】黃志賢,無電鍍錫鎳鈷於銅底材之動力學研究,逢甲大學化學工程研究所碩士論文(2000)【4】H.Narcus, Metal Finishing,45,64(1947)【5】A.E.Carhill, AES Pro.44,130(1957)【6】R.J.Zebliski, U.S. Patent 3,672,938,(June 27,1972)【7】J.Bielinski and K.Kaminski, Surf. and Coat. Tech. 31,223(1987)【8】洪愛娜,電路板會刊第十期, pp.32-36(2000)【9】郭淑真,無電鍍法製備鈷∕銅多層薄膜磁阻材料之研究, 逢甲大學化學工程研究所碩士論文(1998)【10】S.H.Smith, Metal Finishing,47,pp.60(1979)【11】L.Hexing, C.Haiying, D.Shuzhong, Y.Jianshu, and D.Jing-Fa, “Study on the crystallization process of Ni-P amorphous alloy”, Applied Surface Science,125,pp.115-119(1998)【12】Zhang, Bangwei, and Xie, Haowen,“Effect of alloying elements on the amorphous formation and corrosion resistance of electroless Ni-P based alloys”,Materials Science and Engineering, A281,pp.286-291(2000)【13】M.R.Lukes, Plating,15,pp.969(Oct.1964)【14】A.Malecki, and A.Micek-Ilnicka,“Electroless nickel plating from acid bath”,Surface and Coating Technology,123,pp.72-77(2000)【15】宋抑恆“鍍鎳的理論與實務”,徐氏基金出版(1989)【16】百稼企業股份有限公司“Process Control Plan, No.v9004012”【17】金進興“無接著劑之軟板材料”, 電路板會刊第十一期【18】J.F.D‘Amico, M.A.DeAngelo, J.F.Henrickson, J.T.Kenny and D.J. Sharp, J. Electrochem, Soc. Vol.118, No.10(1971)【19】B.K.W.Baylis, A.Bushttil, N.E.Hedgecock, and M.Schlesinger J.Electrochem. Soc. Vol.123, No.3(1976)【20】黃振忠,電子顯微鏡探測光照射對無電鍍金原子凝聚與成長的影響, NSC 80-0208-M033-17【21】S.L.Chow, N.E.Hedgecock, M.Schlesinger, and J. Electrochem. Soc. Vol.119, No3(1972)