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研究生:翁銘隆
研究生(外文):Mean-Long Oung
論文名稱:EEPROM記憶元特性的理論分析與研究
論文名稱(外文):Theoretical Study and Analysis for EEPROM Memory Cell Characters
指導教授:陳勝利陳勝利引用關係陳勛祥陳勛祥引用關係
指導教授(外文):Shen-Li ChenHsun-Hsiang Chen
學位類別:碩士
校院名稱:大葉大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:43
中文關鍵詞:揮發性記憶體非揮發性記憶體臨界電壓抹除寫入
外文關鍵詞:Volatile MemoryNonvolatile MemoryThreshold VoltageEraseWrite
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近幾年來,拜半導體技術的蓬勃發展,記憶體IC在市場上已具舉足輕重的地位。一般而言,記憶體可區分為揮發性記憶體(Volatile Memory)和非揮發性記憶體(Nonvolatile Memory)兩種。所謂的揮發性記憶體乃指記憶體在電源消失後即無法保存原來的資料,諸如DRAM、SRAM等即是屬於揮發性記憶體;而非揮發性記憶體乃指記憶體在電源消失後仍能保存其原來的資料:EPROM、EEPROM及FLASH等即是屬於非揮發性記憶體。其中EEPROM雖然其Memory Cell和其他非揮發性記憶體比較起來實在不小,然而其優良的可靠性及耐久性(Endurance)特性相較於其他非揮發性記憶體仍佔有優勢;IC卡、電話卡等類的應用產品仍以其為主,而在軍事導彈應用上,EEPROM也是最可靠的選擇。
一般EEPROM在開發上所遭遇到的幾個關鍵性技術,分別為Memory Cell design、High Voltage Charge Pump design、Serial I/O circuit design、Sense Amp. design及Memory Cell可靠度的考量等。
這些包括製程、元件及線路設計等的種種技術在全盤開發整合後,才可設計出此類產品。然而,在設計之初,如能透過理論模型分析計算,對某些元件的特性預先加以考量,做出正確的設計方向,將可減少設計上的風險。

Abstract
Although EEPROM has larger memory size, its reliability and endurance characteristics are better than other non-volatile memories, such as FLASH-EPROM products. Consequently, many applications still use it, such as IC cards、smart cards and phone cards, and so on. Generally speaking, there are some important technologies needed to consider during EEPROM products development, especially in memory cell, For the research of EEPROM memory cell, we focus on the threshold voltage shift due to programming or erasing operation, data retention, and data endurance.
The non-volatile memory devices have the capability to store the information. The data storage is mainly determined by the charges on the floating gate. Such that if the change of charge on the floating gate can be accurate to predict, then the shifting of device threshold voltage and the data storage or not can be discriminated. Therefore, in this study, we will investigate the threshold voltage alteration during the programming and erasing operation of EEPROM memory.

Contents
Chinese Abstract ……………………………………………………iv
English Abstract………………………………………………………v
Acknowledgement ………………….…………………………………vi
Contents………………………………………………………………vii
Figure Lists …………………………………………………………ix
Table Lists……………………………………………………………xi
Chapter 1. Introduction to EEPROM Technology…………………1
1.1 EEPROM Background……………………………………………1
1.2 Fowler-Nordheim (F-N) Tunneling…………………………1
1.3 Operation of Device…………………………………………3
Chapter 2. Device Model Building…………………………………4
2.1 Calculation of Tunnel Current……………………………4
2.2 Calculation of Coupling Ration …………………………4
2.3 Calculation of Vtun(t) ……………………………………7
2.4 Calculation of Vt(t) ………………………………………9
Chapter 3. Experimental Results and Comparison with The Device Model……………………………………………………………………11
3.1 Description of Device Process Flow ………………………11
3.2 Experimental Results …………………………………………13
Chapter 4. EEPROM Memory Reliability …………………………14
4.1 Hot Carrier Effect…………………………………………14
4.2 Breakdown Lifetime Evaluation …………………………15
4.3 Endurance Cycling Test……………………………………16
4.4 Data Retention / High Temperature Storage …………17
Chapter 5. Conclusion………………………………………………18
References ……………………………………………………………19

Reference
[1] A. Modeli, and B. Ricco, “Electric Field and Current Dependence of SiO2 Intrinsic Breakdown,” in IEDM, pp148, 1984.
[2] M. Lenzlinger, and E. H. Snow, “Fowler-Nordheim tunneling into
thermally grown SiO2.” in J. Appl. Phys, vol. 40, pp278, 1969.
[3] P. I. Suciu, B. P. Cox, D. D. Rinerson, and S. F. Cagnina , “Cell
Model for EEPROM floating-gate memories,” in IEDM Tech. Dig, pp737, 1982.
[4] A. Kolodny, S. T. K. Nieh, B. Eitan, and J. Shappir, “Analysis and
Modeling of Floating — Gate EEPROM Technology,” in IEEE Transactions on Electron Device, June 1986.
[5]C. Hu, “Thin Oxide Reliability,” in International Electron
Devices Meeting Technical Digest, 1985.
[6]W. S. Johnson, G. Perlegos, A. Renninger, G. Kuhn, and T. R.
Ranganath, “A 16Kb Electrically Erasable Nonvolatile Memory,”
in IEEE International Solid-State Circuits Conference Digest
of Technical Papers, 1980.
[7]B. Euzent, N. Boruta, J. Lee, and C. Jenq, “Reliability
Aspects of a Floating Gate EEPROM,” in Proceedings of the
International Reliability Physics Symposium, 1981.
[8]K. Naruke, S. Taguchi, and M. Wada, “Stress Induced
Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide
Thickness,” in International Electron Devices Meeting Technical
Digest, 1988.

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