臺灣博碩士論文加值系統

摘 要

本篇論文主要是利用數值模擬方法深入瞭解功率雙擴散金氧半電晶體和絕緣閘雙極性電晶體在衛星通訊應用上的輻射效應，然後提出一個改善元件輻射容忍力的方法。本篇論文利用元件模擬將重離子照射在許多不同形式結構的功率金氧半電晶體和絕緣閘雙極性電晶體，從中分析輻射效應的內部物理機制，如single event burnout (SEB) 和 single event latchup (SEL)。
本篇論文的第一部份是顯示功率金氧半電晶體(包括雙擴散金氧半電晶體和槽狀閘極金氧半電晶體)的輻射效應，然後在不影響操作特性下發展抗輻射的元件結構。在此部分，將探討兩種垂直通道結構的功率金氧半電晶體。第一種結構是雙擴散金氧半功率電晶體，第二種結構是槽狀閘極金氧半電晶體。
本篇論文的第二部份是利用元件模擬學習功率絕緣閘雙極性電晶體(包括平面閘極絕緣閘雙極性電晶體和槽狀閘極絕緣閘雙極性電晶體)的輻射效應，然後利用製程上的修正，提出改善功率絕緣閘雙極性電晶體輻射效應的方法。在此部分，將探討兩種垂直通道結構的功率絕緣閘雙極性電晶體。第一種結構是平面閘極絕緣閘雙極性電晶體，第二種結構是槽狀閘極絕緣閘雙極性電晶體。

Abstract

In this thesis, we use the numerical simulation to provide insights into the radiation effects on double-diffused metal-oxide-semiconductor (DMOS) power transistors and insulated-gate bipolar transistors (IGBTs) for satellite communication applications and improve the radiation tolerance of these devices. By simulation, several types of power metal-oxide-semiconductor field-effect-transistors (MOSFETs) and IGBTs were irradiated with heavy ions to analyze the physical mechanisms of radiation effects, such as single event burnout (SEB) and single event latchup (SEL).
The first part of the thesis shows the radiation effects on power MOSFETs (DMOS and trench-gate MOS (UMOS)) and then develops structures to harden power MOSFETs without sacrificing normal performance. In this part, two vertical channel power MOSFET structures have been investigated. The first structure is the DMOS power transistors. The second structure is the UMOS.
Finally, the radiation effects on power IGBTs (planer gate and trench gate IGBTs) were studied through two-dimensional device simulations to find the solution to harden power IGBTs against radiation. In this part, two vertical channel power IGBT structures have been investigated. The first structure is the conventional planer gate IGBT. The second structure is the trench gate IGBT.

目 錄

中文摘要i
英文摘要 ii
誌謝iii
目錄iv
圖目錄ix
表目錄xx
第一章 緒論1
1.1 研究背景1
1.2 研究動機2
1.3 論文組織2
第二章 基本原理4
2.1 摘要4
2.2 SEB原理4
2.2.1 重離子的數值分析5
2.2.1.1 離子的軌跡5
2.2.1.2 離子所產生的線性能量轉換5
2.2.2 電流感應累增模型（CIA Model）5
2.2.3 回授機制（Feedback Mechanism）8
2.3 SEL原理9
2.3.1 IGBT閂鎖回授機制9
2.3.2 SEL回授機制11
2.3.2.1 SEL回授的四個過程12
第三章 VDMOS結構的SEB現象23
3.1 前言23
3.2 基本模擬23
3.2.1 元件結構及崩潰電壓23
3.3 SEB模擬分析25
3.3.1 分析結構B發生SEB現象時，電場、電流線及電位線的變化過程25
3.3.2 分析結構B無發生SEB現象時，電場、電流線及電位線的變化過程26
3.3.3 分析結構E的偏壓效應27
3.3.4 分析結構E的位置效應27
3.3.5 分析結構E無發生SEB現象時，電場的變化過程28
3.3.6 分析結構E發生SEB現象時，電場的變化過程28
3.3.7 利用結構E，分析漸進式CIA模式的原理29
3.3.8 離子撞擊位置的敏感性分析29
3.4 SEB改善結果模擬分析30
3.5 結論31
第四章 VIGBT的SEL現象53
4.1 前言53
4.2 基本特性模擬54
4.2.1 元件結構及崩潰電壓54
4.3 SEL模擬分析56
4.3.1 分析結構E的偏壓效應56
4.3.2 分析結構E的位置效應57
4.3.3 分析結構E無發生SEL現象時，電流線的變化過程58
4.3.4 分析結構E發生SEL現象時，電流線的變化過程58
4.3.5 分析比較結構A、E之間的輻射過程59
4.4 SEL改善結果模擬分析60
4.5 結論61
第五章 UMOS的SEB現象79
5.1 前言79
5.2 基本特性模擬79
5.2.1 元件結構及崩潰電壓79
5.3 SEB模擬分析80
5.3.1 分析結構D的偏壓效應80
5.3.1.1 分析比較結構C及D的偏壓效應81
5.3.2 分析結構D的位置效應82
5.3.3 分析結構D發生SEB現象時，電場、電流線及電位線的變化過程82
5.3.4 分析結構D無發生SEB現象時，電場、電流線及電位線的變化過程83
5.3.5 分析結構E的偏壓效應84
5.3.6 分析結構E的位置效應84
5.3.7 分析結構E發生SEB現象時，電場、電流線及電位線的變化過程85
5.3.8 分析結構E無發生SEB現象時，電場、電流線及電位線的變化過程85
5.4 SEB改善結果模擬分析86
5.5 結論87
第六章 UMOS-IGBT的SEL現象111
6.1 前言111
6.2 基本特性模擬111
6.2.1 元件結構及崩潰電壓111
6.3 SEL模擬分析112
6.3.1 分析結構D的LET效應112
6.3.2 分析結構D的偏壓效應112
6.3.3 分析結構D的位置效應113
6.3.4 分析比較結構B、C之間的輻射過程113
6.3.5 分析比較結構C、D之間的輻射過程114
6.3.6 分析結構E的LET效應115
6.3.7 分析比較結構A、E之間的輻射過程115
6.3.8 分析比較結構E、D之間的輻射過程116
6.4 SEL改善結果模擬分析116
6.5 結論117
第七章 結論132
參考文獻134

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