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研究生:簡茂全
研究生(外文):Mao-Chuan Chien
論文名稱:互補型金氧半高速電壓比較器
論文名稱(外文):A CMOS High-speed Voltage Comparator
指導教授:劉紹宗
學位類別:碩士
校院名稱:逢甲大學
系所名稱:電機工程所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:57
中文關鍵詞:自我偏壓互補型金氧半傳輸延遲時間磁滯電壓高速比較器.
外文關鍵詞:CMOSSelf-biasingPropagation delay timeHysteresis voltageHigh-speed comparator.
相關次數:
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本論文旨在設計一個互補型金氧半高速電壓比較器。在論文中提出的比較器使用P型差動對當輸入級以提升更多的增益,與一般常用N型差動對當輸入級有所不同,然後再利用一個自我偏壓電路之不受溫度和供應電壓變化的影響,以提供穩定的3.5V偏壓,藉此兩者達成高速比較器的特性。
此比較器選用聯電0.5微米、兩層poly、三層metal、n型井、CMOS製程。其特色在於當供應電壓為5V時,有著較少的傳輸延遲時間為36ns,和較快的響應時間為41ns,和磁滯電壓範圍為5mV到11mV,而整個電路的功率消耗在4mW以下。
This thesis presents a design of an innovational high-speed CMOS voltage comparator. The comparator proposed in this thesis uses a p-type differential pair as input stage to provide more gains which differs from using an n-type differential pair. Furthermore, the comparator makes use of a self-biasing circuit to provide a stable 3.5 V output voltage. This output voltage is not affected by the variations of temperature or supplies. By utilizing the designed circuit, high-speed can be achieved.
The designed comparator is fabricated by UMC 0.5mm double-poly, triple-metal, N-well CMOS process. The comparator can achieve less propagation delay time (36 ns), fast response time (41 ns), hysteresis voltage between 5 mV and 11 mV, and low power dissipation (4 mW).
中文摘要..………………………………………………………………..…. i
英文摘要..………………………………………………………………….. ii
誌謝..………………………………………………………………………. iii
目錄…………………………………………………………………………iv
圖目錄……………………………………………………………………... vi
表目錄..……………………………………………………………………..ix
縮寫及符號對照表..…………………………………………………….…..x
第一章緒論
1.1 前言……………………………………………………………1
1.2 設計流程………………………………………………………3
1.3 模型參數………………………………………………………4
1.4 論文內容………………………………………………………5
第二章高速電壓比較器電路架構
2.1  前言……………………………………………………………6
2.2  電壓比較器……………………………………………………7
2.2.1 比較器原理………………………….……………………..7
2.2.2 輸入抵補電壓…………………………………………….10
2.2.3 傳輸延遲時間…………………………………………….11
2.3 單級比較器……………………………………………………12
2.3.1 Current-Sink 反相器….………………………………….12
2.3.2 差動輸入級比較器………………………………………...14
2.4 兩級比較器……………………………………………………18
2.5  差動輸入級…….…………………….….……….……………22
2.6 比較器的磁滯現象……………………………………………25
2.7 偏壓電路………………………………………………………32
2.8 輸出級…………………………………………………………36
第三章 整體電路與模擬結果
3.1 前言……………………………………………………………39
3.2 整體電路與模擬………………………………………………39
第四章 佈局…………………………………………………………….50
第五章結論…………………………………………………………….52
參考文獻…………………………………………………………………...54
作者簡介…………………………………………………………………...57
[1]Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Oxford, New York, 1987.[2]David A. Johns and Ken Martin, Analog Integrated Circuit Design, Wiley, Canada, 1997.[3]R. Gregorian, Introduction to CMOS OP-Amps and Comparators, Wiley, Canada, 1999.[4]B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.[5]W. S. Chu and K. Wayne Current, “A Rail-to-rail Input-Range CMOS Voltage Comparator,” IEEE J. Solid-State Circuits pp. 160-163, 1997.[6]A. Hastings, The Art Of Analog Layout, Prentice Hill, New Jersey, 2001.[7]J. T. Wu and Bruce A. Wooley, “A 100-Mhz Pipelined CMOS Comparator,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 1379-1385, Dec. 1988.[8]Kh. Hadidi and Cabor C. Temes, “ A High-resolution Low offset and High-speed Comparator,” in Custom Integrated Circuits Conf., vol. 16, no. 1, pp. 1-4, 1992.[9]B. Razavi and Bruce A. Wooley, “Design Techniques For High-speed High-resolution Comparator,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992.[10]M. Bruccoleri and P. Cusinato, “Offset Reduction Technigue For Use With High Speed Comparator,” IEEE J. Solid-State Circuits, vol. 32, no. 13, pp. 1193-1194, June 1996.[11]G. M. Yin, F. O. Eynde and W. Sansen, “A High-speed CMOS Comparator With 8-b resolution,” IEEE J. Solid-State Circuits, vol. 27, no. 2, pp. 208-211, Feb. 1992.[12]D. Y. Kim, O. S. Kwon and J. H. Bang, “The Design Of High Speed Amplifier Circuit For Using in the Analog Subsystems,” IEEE J. Solid-State Circuits, pp. 485-488, 1992.[13] Hoi-Jun Yoo, Seung-Jun Lee, Jeong-Tae Kwon, Wi-Sik Min and Kye-Hwan Oh, “A Precision CMOS Voltage Reference With Enhanced Stability for the Application to Advanced VLSI’s,” IEEE J. Solid-State Circuits, pp.1318-1321, 1993.
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