臺灣博碩士論文加值系統

在積體電路中，數位電路是實現晶片功能的最主要部分。邏輯電路又佔了數位電路中的絕大部分。在論文中，首先我們回顧歷史，舉出十多種較為常見的邏輯電路來做簡單的介紹。
然後我們提出基極輸入差動邏輯電路，以往的邏輯電路中只能接固定訊號的基極端在我們的努力下也成為可以接收訊號的輸入端，大幅度的改善了電路設計的靈活性。我們在輸入元件的基極端接上一個推舉電路來避免半導體接面的順向偏壓困擾。基極輸入差動邏輯電路可以在不消耗靜態功率的條件下有互補的全擺幅輸出。
從模擬結果中基極輸入差動邏輯電路被證明比起傳統的差動邏輯電路還要高速和低功率。在兩個輸入以上邏輯閘中，消耗功率和延遲時間的乘積改善了百分之十三以上。為了驗證基極輸入差動邏輯電路是否如同模擬結果，我們設計了一個測試晶片，晶片是一個頻率合成器其中的可程式化除頻器是使用基極輸入差動邏輯電路設計的，之中的八輸入基極輸入差動邏輯閘在模擬中可以操作在二十億赫茲的高速。測試晶片目前正在台積電製造中。

In VLSI circuits, the digital circuits are the important parts in a chipset. The logic circuits occupy the almost of digital circuits. In this paper, we make a logic circuits history review. Some popular logic circuits will be introduced.
Then the bulk input differential logic (BIDL) is presented. The bulk terminals of conventional circuits always connect to highest or lowest voltage. The bulk input differential logic circuits make the bulk terminals able to receive signals. It improves the logic design flexibility into a wide margin. A boost circuit is employed to the bulk terminal of the input device to avoid the p/n junction forward bias problem. The BIDL can generate a pair of complementary full-swing output signals without dc power dissipation.
It is shown that the BIDL has better speed and power performance compared to the conventional differential logic circuits in simulation results. In more than two inputs logic gates, the improvement of power-delay product is more than thirteen percentages. To verify the BIDL is good as simulation results, we design a test chip. The chip is a frequency synthesizer which uses the BIDL in the prescaler design. In the prescaler, an 8-inputs BIDL gate can operate at 2GHz in TSMC 0.25um process simulation. The test chip is being fabricated.

摘要 i
Abstract ii
致謝 iv
List of Contents v
List of Figures vii
List of Tables ix
Chapter 1 Introduction………………………………………………………..…… 1
1.1 Static CMOS logic family…………………………………………………..…… 2
1.2 Pseudo NMOS logic family…………………………………………………….... 4
1.3 Dynamic CMOS logic family…………………………………………………..... 6
1.4 Pass transistor and transmission gate logic………………………………………. 8
1.5 Differential logic family………………………………………………………….. 9
1.5.1 Differential cascode voltage switch logic…………...………………………9
1.5.2 Full-swing differential logic………………………………………………..10
1.5.3 Differential current switch logic……………………………………………11
1.5.4 Current sensing differential logic…………….…………………………….12
1.5.5 Sample-set differential logic……………………………………………….13
1.5.6 Latched CMOS differential logic…………………………………………..14
1.5.7 Enable/disable CMOS differential logic…………………………………...15
1.5.8 Low-voltage differential current switch logic…………………...…………16
1.6 Threshold logic gate……………………………………………………………...17
Chapter 2 Bulk Input Differential Logic…………………………………………..18
2.1 Current latched sense amplifier…………………………………………..………19
2.2 Boost circuits…………………………………………………………………..…20
2.3 Multiple inputs boost circuit……………………………………………………...23
2.4 The BIDL topology…………………………………………………………....…24
Chapter 3 Design Examples………………………………………………………..26
3.1 BIDL AND2/NAND2 gate……………………………………………………….26
3.2 BIDL XOR2/NXOR2 gate……………………………………………………….27
3.3 BIDL OR3/NOR3 gate……………………………………………………...……29
3.4 BIDL AND4/NAND4 gate……………………………………………………….30
3.5 BIDL MUX2 gate…………………………………………………………...……32
3.6 BIDL OAI (Q=A．(B+C+D)) gate……………………………………………….34
3.7 BIDL AOI (Q=A+BC+BD+DE) gate……………………………………………35
3.8 BIDL AOI (Q=A+BCDE) gate……………………………………………….….37
3.9 BIDL AND5/NAND5 gate………………………………………………………39
3.10Simulation results comparison…………………………………………………..41
3.10.1 Logic circuits with no sense amplifier……………………………………41
3.10.2 Logic circuits with sense amplifier……………………………………….42
Chapter 4 Frequency synthesizer……….…………………………………………44
4.1 Circuit design………………………..……………………………………...……44
4.1.1 Voltage Control Oscillator………..………………………………………..44
4.1.2 Phase Frequency Detector………………………………………………….45
4.1.3 Charge Pump……………………………………………………………….46
4.1.4 Prescaler……………………………………………………………………47
4.2 Implementation…………………...………………………………………………48
Chapter 5 Conclusions and Future work………………………………………….51
5.1 Conclusions………………………………………………………………………51
5.2 Future Work…………………………………………………………………...…52

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