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研究生:蘇烜毅
研究生(外文):Hsuan-Yi Su
論文名稱:隱藏式行再生低功率內嵌式假靜態記憶體
論文名稱(外文):Low-Power Embedded Pseudo SRAM Using Hidden Column Refresh Method
指導教授:黃弘一
指導教授(外文):Hong-Yi Huang
學位類別:碩士
校院名稱:輔仁大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:56
中文關鍵詞:行再生內嵌式記憶體隱藏式行再生
外文關鍵詞:Column RefreshEmbedded MemoryHidden Refresh
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這篇論文主要提出了一個方法,對2P2N記憶體採用行方向做再生( Refresh ) 動作,此方法會瞬間將記憶體一行中,所有儲存點做更新的動作。此方法和傳統採用列方向做再生動作比較起來,所消耗的功率較少,且採用行再生(Hidden Refresh)方式,在設計2P2N記憶體單元時,並不需要額外考慮到PMOS電晶體與NMOS電晶體在漏電流上的比例關係。一般設計中,輸入輸出的規格上,完全和SRAM相同,不需要額外考慮到Refresh的動作。此外,在製程上,此種設計方式,也可以採用一般的標準CMOS製程,在小面積上實現出一個內嵌式記憶體。

A column hidden refresh technique is proposed for the 2P2N SRAM design. All of the storage nodes of the 2P2N cells in the same column are refreshed simultaneously. The dissipated power of the column hidden refresh is proved to be much less than that of the traditional row hidden refresh. Using the hidden refresh method, the 2P2N cells can be designed without considering the ratio of the leakage current of the PMOS access transistors and the NMOS storage transistors. The novel design has the same I/O specification as the SRAM. Moreover, it can be fabricated in standard CMOS process as a small-area embedded memory.

目錄
頁次
中文摘要..................................................i
英文摘要..................................................ii
致謝......................................................iii
目錄......................................................v
表目錄....................................................viii
圖目錄....................................................ix
第一章 導論..............................................1
1.1 研究計畫之背景........................................1
1.2 簡介..................................................1
1.3 先前所提出的方法......................................6
1.3.1 Static Random Access Memory Cell....................6
1.3.2 Loadless Four-Transistor SRAM.......................7
1.3.3 Tunneling Based SRAM................................8
1.4 Refresh的方法簡介.....................................10
1.4.1 External Logic Refresh..............................10
1.4.2 Internal Logic Refresh..............................10
1.4.3 Self-Refresh Refresh................................11
1.4.4 Quasi-Static SRAM...................................11
1.4.5 Hidden Refresh......................................11
1.5 各種DRAM cell 之Internal Refresh的方法................11
1.4.1 4N DRAM Cell........................................11
1.4.2 2P2N DRAM Cell......................................12
1.4.3 1T DRAM Cell........................................12
1.6 Refresh先前技術介紹...................................13
1.6.1 Hidden Refresh of A Dynamic Random Memory...........13
1.6.2 Transparent-Refresh DRAM(TReD) Using Dual Port DRAM Cell......................................................14
1.7 論文組織..............................................16
第二章 低功率2P2N靜態記憶體..............................17
2.1 2P2N Pseudo SRAM......................................17
2.2 Column Hidden Refresh Method..........................19
2.3 Comparison Result.....................................24
第三章 整體架構與模擬結果................................30
3.1 整體架構..............................................30
3.1.1 整個晶片架構........................................30
3.1.2 控制單元CTLBUF......................................31
3.1.3 記憶體區域CELL32X8..................................33
3.1.4 記憶體單元..........................................33
3.1.5 多工器..............................................34
3.1.6 輸入輸出緩衝器......................................34
3.1.7 解碼器(ROW32 &COL8)..............................35
3.1.8 I/O Enable..........................................36
3.1.9 Timing Control......................................37
3.1.10 更新位址產生器.....................................37
3.1.11 Charge Pump Circuit................................38
3.2 模擬結果..............................................40
第四章 晶片Layout與測試結果..............................42
4.1 晶片佈局..............................................42
4.1.1 1位元CELL32X8電路佈局...............................43
4.1.2 記憶體單元佈局......................................43
4.1.3 輸入輸出緩衝器佈局..................................44
4.1.4 解碼器佈局..........................................45
4.1.5 CHANGE PUMP佈局.....................................46
4.2 Post Layout Simulation................................47
4.3 測試晶片..............................................48
4.4 量測結果..............................................49
第五章 總結與未來研究方向................................52
5.1 總結..................................................52
5.2 未來研究方向..........................................52
參考文獻..................................................54
簡歷......................................................56

[1] Marr, Ken, Manning, and H. Montgomery, “Static Random Access Memory,” U.S. Patent 6044011, 2000.
[2] T. Iwata, “A evaluation of memory cell leakage at 16Mbit DRAM,” in Proc. Institute of Electronics Information and Communication Engineers, Mar 1995.
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[12] K. Sato, K. Kenmizaki, S. Kubono, T. Mochizuki, H. Aoyagi, M. Kanamitsu, S. Kunito, H. Uchida, Y. Yasu, A. Ogishima, S. Sano, and H. Kawamoto, “A 4-Mb pseudo SRAM operating at 2.6+or-1 V with 3- mu A data retention current,” IEEE J. Solid-State Circuits, vol. 26, pp. 1556 —1562, Nov. 1991.
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