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研究生:吳汀源
研究生(外文):Ting-Yuan Wu
論文名稱:菲特比IP之解碼器使用返回式內容定址法
論文名稱(外文):The Trace Back IP of Viterbi Decoder Using Content-Addressable Scheme
指導教授:金明浩金明浩引用關係柯松源
指導教授(外文):Ming-Haw JingSung-Yuan Ko
學位類別:碩士
校院名稱:義守大學
系所名稱:資訊工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:70
中文關鍵詞:菲特比返回式內容定址法迴旋碼
外文關鍵詞:ViterbiContent-AddressableConvolutional code
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迴旋碼 (convolutional code) 已經被廣泛的應用在通訊系統和行動電話上面。迴旋碼的成功因素在於有效率和簡單的解碼,其使用菲特比演算法 (Viterbi algorithm) 找出最大相似路徑 (maximum-likelihood)。因為菲特比解碼器有順前向錯誤修正 (forward error correction) 的功能,很多的菲特比解碼器在過去已經被實現,且應用在不同的領域中。
本論文首先要實現菲特比演算法,其實作上包括下面四個基本單元: 轉移距離單元 (transition metric unit),加比選單元 (add-compare-select unit),存活路徑記憶單元 (survivor memory unit),以及回溯單元 (trace-back unit)。
在回溯單元中,有暫存器交換 (register-exchange) 及回溯 (trace-back) 兩種方法,用以設計儲存活路徑之記憶及回溯追蹤功能。經分析,在時序的延遲,效率和系統之設計上,這兩種方法都各有其缺點,如暫存器交換方法因連線的需要而佔用較大的面積,而對不同的編碼器就必須有不同的設計。而回溯法雖然可以設計給不同的編碼器使用,卻無法達到高速的要求。
在這篇論文當中,我們提出一種依內容定址的方法成功地解決了這些缺點,於FPGA板上完成實作及驗證,並對其設計於系統上的效率做了明確的分析,成效優異。

The convolutional codes have been widely applied on digital communication and cellular phone. The reasons of this success are their efficiency and simple decoding with maximum-likelihood (ML) using Viterbi algorithm (VA). Many Viterbi decoders have been implemented in the past for various applications by the forward error correction (FEC) capability of the decoders.
VA is an efficient method for decoding the convolutional code. The implementation of VA can be divided into four units, the transition metric unit (TMU), the add-compare-select unit (ACSU), the survivor memory unit (SMU), and the trace-back unit (TBU). The high-speed implementation of the VA has be implemented.
The register-exchange method and trace-back are two methods for survivor memory management. Unfortunates, each of these two methods has its own drawbacks on timing delay, efficiency, and system design. The register-exchange method requires a large amount of area for wiring, and is often hard wired to particular trellis. Although the trace-back method can be designed to serve different trellises, it also takes a longer delay.
In this thesis, we present a new method successful solve these drawbacks, the presented decoding scheme uses content-addressable trace-back method. This scheme has implemented in a FPGA based test-bench for verification. The efficiency on our design has a major breakthrough.

Contents
Acknowledgement I
摘 要 II
Abstracts III
Contents IV
Chapter 1 Introduction 1
1.1 The Objective and Motivation 1
1.2 The Proposed Methods 3
1.3 Organization of Thesis 3
Chapter 2 The convolutional code 5
2.1 The Encoder 6
The State Diagram 8
2.2 Decode 9
2.2.1 Trellis diagram 10
2.2.2 The Viterbi Algorithm 12
2.2.3 The modules in the Viterbi decoder 13
2.3 Example of convolutional code using Viterbi algorithm 13
Encode: 14
Decoder: 14
No noise: 14
With noise: 17
Chapter 3 The Survivor Path Memory Management 18
3.1 Introduction to survivor memory 18
3.2 The Register-Exchange Method 19
3.3 The Trace-Back Method 21
3.4 The proposed trace-back method 23
3.5 System analysis 26
Chapter 4 Design Approaches 28
4.1 System development methodology 28
4.2 System environment and interface 29
4.3 Software simulation 29
4.4 Gate-level emulation system 31
4.5 Prototyping system and test-bench 32
Chapter 5 System implementation 35
5.1 The algorithm of the proposed decoder 36
5.2 The Transition Metric Unit (TMU) module 37
5.3 The Add-Compare-Select Unit (ACSU) module 37
5.4 The Survivor Memory Unit (SMU) module 38
5.4.1 The Buffer Design 38
5.4.2 The Single Buffer for SMU 39
5.4.3 The Dual Buffer for SMU 39
5.4.4 The Front Buffer for SMU 40
5.5 The content-Addressable scheme 41
5.6 The timing controller module 45
Chapter 6 The Result and Conclusion 46
6.1 The Result 46
6.2 Conclusion 49
6.3 Future work 50
References 51
Appendix 53

References
[1] G. D. Forney, “The Viterbi Algorithm”, Proc. IEEE, vol. 61, pp.268-278, Mar. 1973.
[2] G. D. Forney, “Maximum-likelihood sequence estimation of digital sequences in the presence of intersymbol interference,” IEEE Trans. Information Theory, Vol. IT-18, 1972, pp.363-378.
[3]. Peter J. Black and Teresa H. -Y. Meng, “Hybrid Survivor Path Architecture for Viterbi Decoders”, Information Systems Laboratory, Stanford University, CA94305, 1993 IEEE.
[4] Gennady Feygin and P. G. Gulak, “Architectural Tradeoffs for Survivor Sequence Memory Management in Viterbi Decoders,” IEEE Transactions on communications, VOL. 41, NO3, March 1993.
[5] Stephen B. Wicker, “Error Control Systems for Digital Communication and Storage”, Prentice-Hall International, Inc, pp.264-303, 1995.
[6] P. ELIAS. “Coding for Noisy Channels” IRE Conv. Record, Part 4, pp. 37-47, 1955.
[7] C. E. SHANNON, “A Mathematical Theory of Communication”, Bell System Technical Journal, Vol. 27, pp. 379-423 and pp. 623-656, 1948.
[8] J. M. WOZENCRAFT and B. REIFFEN, Sequential Decoding, Cambridge, MA: MIT Press, 1961.
[9] J. L. MASSEY. Threshold Decoding, Cambridge, MA: MIT Press, 1963.
[10] R. M. FANO. “A Heuristic Discussion of Probabilistic Decoding”, IEEE Transactions on Information Theory, IT-9, pp. 64-74, April 1963.
[11] F. JELINEK. “A Fast Sequential Decoding Algorithm Using a Stack”, IBM Journal of Research and Development, Vol. 13, pp.675-685, November 1969.
[12] A. J. VITERBI. “Error Bounds for Convilutional Codes and an Asymptotically Optimum Decoding Algorithm,” IEEE Transactions on Information Theory, Vol. IT-13, pp.260-269, April 1967.
[13] J. K. OMURA. “On the Viterbi Decoding Algorithm,” IEEE Transactions on Information Theory, Vol. IT-15, pp. 177-179, January 1969.
[14] Robert J. McEliece “The theory of information and coding A mathematical framework for communication”, Addison-Wesley Pulishing Company, Inc. 1997, pp. 200-228.
[15] Stephen G. Wilson “Digital Modulation and Coding”, Prentice-Hall International, Inc, 1996, pp. 550-637.
[16] G. D. FORNEY. JR. “ Convolutional Codes II: Maximum Likelihood Decoding,” Information and Control, Vol. 25, pp.222-266, July 1974.
[17] R. M. Orndorf et al., Viterbi Decoder VLSI Integrated Circuit for Bit Error Correction. Anaheim, CA: Rockwell International, Dec. 1981.
[18] C. B. Shung et al., “Implementation issues for the design of a rate 8/10 trellis code for partial response channels,” in Third IBM Workshop ECC, San Jose, CA, Sept. 1989.
[19] C. M. Rader, “Memory management in a Viterbi Algorithm,” IEEE Trans. Commun, vol. 29, pp.1399-1401, Sept. 1981.
[20] O. Collins and F. Pollara, “Memory management in traceback Viterbi decoders,” TDA Prog. Rep. 42-99, Jet Prop. Lab., Pasadena, CA, Nov. 1989.
[21] H. A. Bustamante, et al., “Stanford telecom VLSI design of a convolutional decoder,” in IEEE Conf. Military Commun., vol. 1, pp. 171-178, Boston, MA, Oct. 1989.
[22] T.K. Truong, Ming-Tang Shih, Irving S. Reed, E.H. Satorius, “A VLSI design for a Trace-Back Viterbi decoder”, IEEE Trans. Commun. , pp. 616-624, vol. 40, no. 3, Mar. 1992.
[23] Stephan Schulz, Jerzy W. Rozenblit, “Model-Based codesign,” IEEE Computer, August 1988, pp60-67.
[24] Altera Inc., “MAX+PLUS II VHDL”, Manual.
[25] Altera Inc., “MAX+PLUS II AHDL”, Manual.
[26] Bupesh Pandita, Subir K Roy, “Designed and implementation of Viterbi decoder using FPGAS”, International conference on VLSI design, January 1999.
[27] Wen-Ta Lee, Ming-Hwa chan, Liang-Gee chen, Mao-Chao Lin, ”A Single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm”, IEEE Trans. On consumer electronics, vol. 41, no. 1, Feb. 1995.
[28] Kevin Skahill, “VHDL for programmable logic”, ADDISON WESLEY, 1996.
[29] Rolf Johannesson, Kamil Sh. Zigangirov, "Fundamentals of Convolutional Coding", pp.317-327, 1999.

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