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研究生:周至豪
研究生(外文):Chin-Hao Chou
論文名稱:二維雙正交小波轉換之分離式演算法
論文名稱(外文):A Modified Lifting VLSI Structure For 2-D Biorthogonal Wavelet Transform
指導教授:黃有榕洪惠陽
指導教授(外文):Yu-Jung HuangHuey-Yang Horng
學位類別:碩士
校院名稱:義守大學
系所名稱:電子工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:149
中文關鍵詞:影像處理雙正交小波轉換分離式演算法
外文關鍵詞:Image ProcessBiorthogonal Wavelet TransformLifting
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  • 收藏至我的研究室書目清單書目收藏:2
從小波發展至今,傳統二維離散雙正交小波轉換的超大型積體電路架構都是以遞迴式金字塔演算法為基礎。在此理論基礎上的架構都必須利用插值法的技術去解決因回授而造成的多重資料輸入衝突,如此將會大大的增加電路的複雜度和資料的硬體運算時間。為了避免如此的問題,本篇論文針對分離式的二維離散小波轉換提出了一個有效率的二維串聯式分離式演算法之超大型積體電路架構。此二維架構是建構在一個有效率的一維分離式演算法架構,此一維的架構是根據分離式演算法的資料流程分析而建立的,在文章中我們會介紹分離式演算法架構的優點並和傳統的濾波器架構做比較。之後我們使用Altera Max+plus II來完成一維架構的模擬,並設計出二維的架構。

Since the traditional VLSI architectures of the 2D discrete biorthogonal wavelet transform (DBWT) are based on the recursive pyramid algorithm. They need to apply the interleaving technique to solve the confliction problem of multi-level data input. This will increases circuit complexity and time latency. To avoid from the difficulty, this paper develops an efficient cascaded 2-D lifting VLSI architecture for separable 2-D DBWT. The construction of 2-D architecture is based on an efficient 1-D lifting architecture which is constructed by the data flow graph analysis of a modified lifting algorithm. We show the advantages offered by lifting scheme, compared to classical filter banks based architecture. The 1-D architecture is completely simulated on Altera Max+plus II. The 2-D architecture is designed.

中文摘要..................................................I
英文摘要..................................................III
致謝......................................................IV
目錄......................................................V
圖目錄....................................................VII
表目錄....................................................X
第一章 序論...............................................1-1
1-1研究動機和背景.........................................1-1
1-2 小波轉換(Wavelet Transform)的背景.....................1-2
1-3雙正交小波轉換(BWT)的重要性及優點......................1-7
1-4分離式演算法(Lifting)的優點............................1-8
1-4-1 各種不同1D Lifting方式的比較回顧....................1-10
1-5 本文之Overview........................................1-14
第二章 小波轉換(Wavelet Transform)演算法之回顧............2-1
2-1各種實現WT方法的文獻回顧...............................2-1
2-2小波的理論探討.........................................2-3
2-2-1串級法(cascading method)............................2-5
2-2-2碎形內插數演算法.....................................2-7
2-3線性代數上的觀念.......................................2-8
2-4多重解析度分析(MRA)....................................2-11
2-5二尺度函數(two-scale relations)........................2-13
2-6小波的正交、半正交、平移正交與雙正交性.................2-17
2-7離散小波轉換(Discrete Wavelet Transform )..............2-20
2-8分離式演算法系統(Lifting System).......................2-24
第三章 1D超大型積體電路架構...............................3-1
3-1 1D小波轉換概念........................................3-1
3-2 一維9/7 BWT Filter bank超大型積體電路架構.............3-4
3-3 1D 9/7 BWT分離式演算法之超大型積體電路架構............3-10
3-3-1 1D Pipeline 9/7 BWT分離式演算法之超大型積體電路構...3-16
3-3-2 Split硬體架構.......................................3-21
3-3-3 MAC硬體架構.........................................3-23
第四章 二維的超大型積體電路架構...........................4-1
4-1二維影像壓縮概念.......................................4-1
4-2一階二維9/7 BWT分離式演算法之超大型積體電路架構........4-4
4-3 Split和Lifting列運算架構..............................4-8
4-4 Memory及Counter架構...................................4-10
4-5 濾波電路架構..........................................4-12
4-6 Split和Lifting行運算架構..............................4-14
4-7 三階二維9/7 BWT Lifting超大型積體電路架構.............4-16
第五章 模擬驗證與效能分析.................................5-1
5-1 數位設計概念及流程....................................5-1
5-2 數位邏輯晶片分類......................................5-3
5-3 Altera MAX+plusII 設計流程............................5-4
5-4 二維BWT Lifting Bit數之推估...........................5-6
5-5 9/7 BWT係數分析.......................................5-10
5-6 二維Row/Column Split硬體實現及效能分析................5-11
5-7 Lifting 列/行運算的硬體實現及效能分析.................5-14
5-8 Scaling及Lifting列/行運算的硬體實現...................5-18
5-9 Memory硬體實現和效能分析..............................5-20
5-10 濾波電路硬體實現及效能分析...........................5-22
5-11 二維BWT Lifting超大型積體電路架構....................5-28
5-12 二維硬體架構比較.....................................5-39
5-13 Demo Board 下載驗證..................................5-41
第六章 結論與未來發展.....................................6-1
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