功率消耗在傳統的VLSI晶片設計上是一個被忽略的課題。因為在過去無論是晶片的複雜度或是系統運作的頻率都是非常的低，低到讓我們根本不需要考慮這一個問題。
超大型積體電路在最近幾年裡，因為製程技術不斷提昇、快速的操作頻率、百萬的電晶體做於單一晶片上，低功率消耗已成為一件不可避免而且艱鉅的挑戰。由於低功率應用的需求日益增加使這個問題更加複雜，如筆記型電腦，醫療器材，通訊產品和符合環保要求的桌上型電腦，這些應用都需要降低整體的功率消耗。所以除了操作頻率外，對今日的積體電路設計者而言，功率消耗已經變成了一個非常重要設計的考慮因素。
在這一論文中，我們藉由邏輯結構的分析，找出最好的CUBE，來做預先計算，以控制輸入暫存器的工作。實驗結果顯示，有許多個電路可以逹到減少60%以上，而平均的功率消耗可以減少50.17%。

Power dissipation of VLSI chip is traditionally a neglected subject. In the past, the device density and operating frequency were low enough that it was not a constraining factor in the chips.
As the VLSI process technology continuously improves in recent years, low power consumption has become increasingly important in hand-held communication systems and battery operated equipment, such as laptop computers, multimedia products and cellular phones. In addition to performance, power is becoming a significant concern for designers.
In the thesis, we try to find out the best precomputation logic from a circuit by calculating a power-saving metric, which is determined from the logic analysis of the circuit’s information. As a result, the power reductions achieved by our approach are drastic over 60% for some circuits. We obtain average power reductions of 50.17%.

誌謝 1
Abstract 2
摘要 3
目錄 4
圖 6
表 6
第一章 簡介 7
第一節 問題描述 7
第二節 研究動機與目標 8
第三節 軟體功能及特性 8
第四節 貢獻及成果簡述 9
第五節 內容大綱 9
第二章 背景知識與相關研究 10
第一節 功率消耗的元素和功率消耗模型 10
(一) 轉換或電容功率 11
(二) 內部或短路功率 11
(三) 漏電或靜態功率 11
第二節 轉換次數導致的功率消耗 12
第三節 功率消耗的評估 12
第四節 邏輯合成流程 13
第五節 相關研究 14
第三章 系統架構分析 16
第一節 架構一 16
第二節 架構二 17
第三節 架構三 18
第四節 例子 18
第四章 實作 21
第一節 輸入檔案格式 21
第二節 資料結構 22
第三節 程式流程 22
第五章 演算法 24
第一節 方法一 ON-Set Cube 24
第二節 方法二 OFF-Set Cube 26
第三節 方法三 單互補性 27
第四節 方法四 雙互補性 32
第五節 方法五 相依性 35
第六節 方法六 Cube交集 38
第六章 實驗結果 42
第一節 工作平台及程式語言 42
第二節 結果分析 42
第七章 結論與未來工作 45
參考文獻 46
附錄:使用手冊 51
A. 如何編譯程式 51
B. 如何執行程式 51

[1] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh and M. Papaefthymiou, “Precomputation-based sequential logic optimization for low power,” in IEEE Transactions on VLSI System, Vol. 2, pp. 426-436, December 1994.
[2] Gary Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Publishers, 1998.
[3] A. Mota, J. Monteiro, and A. Oliveira, “Power optimization of combinational modules using self-timed precomputation,“ in Proceedings of the 1998 IEEE International Symposium, Pages 17 -20, vol.2, 1998.
[4] T. Schuele and A.P. Stroele, “Scheduling tests for low power built-in self-test,“ in The 2001 IEEE International Symposium , Vol. 5, 2001.
[5] S. Gerstendorfer and H.-J. Wunderlich, “ Minimized power consumption for scan-based BIST,“ in Test Conference Proceedings International, Pages 77 -84, 1999.
[6] S. J. Wang and Paul, “Structural Presomputation Design Low Power,” in Department of Computer Science National Chung-Hsing University, June 2001.
[7] S. J. Wang and Tedhong, “State Assignment for Low Power Consumption in Sequential Circuits,” in Department of Computer Science National Chung-Hsing University, June 2001.
[8] SIS: A System for Sequential Circuit synthesis is implemented by Electronics Research Laboratory in Department of EE and CS, University of California, Berkley, 4 May 1992.
[9] ESPRESSO: A System for collapse a network and minimize with a two-level minimizer is implemented by Electronics Research Laboratory in Department of EE and CS, University of California, Berkley, 4 May 1992.
[10] Kun-Lin Tsai and Feipei Lai, ”Refunction based Multipartition Architecture for Low Power Circuit Design,” in Department of Computer Science and Information Engineering National Taiwan University, June 2001.
[11] Feipei Lai, ”An Efficient Area-Oriented Algorithm For Low Power Bipartition-Codec Architecture,” in Department of Computer Science and Information Engineering National Taiwan University, June 2001.
[12] M. Damiani and G. De Micheli, “Observability Don’t Care sets and boolean relations,” in IEEE Int’l Conf. Digest of Technical Papers, pp. 502-505, 1990.
[13] Jia-Zheng Liu, De-Sheng Chen, and Bi-Cheng Zhang, “Low Switching Technology Decomposition,” in Department of Computer Science FCU, June 2000.
[14] Z. J. Lemnios and K. J. Gabriel, “Low-Power Electronics,” in IEEE Design & Test of Computers, pp. 8-13, winter 1994.
[15] A. Ghosh, S. Devadas, K. Keutzer, and J. White, “Estimation of Average Switching in Combinational and Sequential Circuits,” in Proceedings of the 27th Design Automation Conference, pp. 253-259, June 1992.
[16] J. Monteiro, S. Devadas, and B. Lin, “A Methodology for Efficient Estimation of Switching in Sequential Logic Circuits,” in Proceedings of the 31st Design Automation Conference, pp. 12-17, June 1994.
[17] Anantha P. Chandrakasan, Samuel Sheng, and Robert W. Brodersen, “Low-power CMOS digital design,” in IEEE Journal of Solid-State Circuits, Vol. 27, pp. 6-13, April 1992.
[18] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, secnod ed., Addison-wesley, 1992
[19] S. Muroga, Y. Kambayashi, H. C. Lai, and J. N. Culliney, ”The transduction method — design of logic networks based on permissible functions,” in IEEE Transactions on Computers, vol. 38, pp. 1404-1424, Oct. 1989.
[20] L. Benini, G. De Micheli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “Glistch power minimization by selective gate freezing,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8 No.3, pp. 287-298, June 2000.
[21] C. Y. Tsui, M. Pedram, and A. Despain, “Exact and approximate methods for switching estimation in sequential logic ircuits,” in Proc. 31st Design Automation Conf., pp. 18-23, June 1994.
[22] K. Roy and S. Prasad, “SYCLOP: Synthesis of CMOS logic for low power applications,” in Proc. Int. Conf. Computer Design: VLSI in Computers and Processors, pp. 464-267, Oct. 1992.
[23] V. Tiwari, S. Malik, and P. Ashar, “Guarded evaluation: pushing power management to logic synthesis/design,” in IEEE Transactions , Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, pp1051 —1060, Oct. 1998.
[24] H. Kapadia, L. Benini, and G. De Micheli, “Reducing switching on datapath buses with control-signal gating,” in IEEE Journal of Solid-State Circuits, Vol. 34, pp. 405 —414, March 1999.
[25] F. Najm, “Transition density, a stochastic measure of activity in digital circuits,” in Proc. 28th Design Automation Conf., pp. 644-649, June 1991.
[26] J. Monteiro, S. Devadas, and A. Ghosh, “Retiming sequential circuits for low power,” in Proc. Int. Conf. Computer-Aided Design, pp. 398-402, Nov. 1993.
[27] L. Benini and G. De Micheli, “State assignment for low power disipation,” in IEEE Journal of Solid-State Circuits, Vol. 30, pp. 258 —268, March 1995.
[28] D. Somasekhar and K. Roy, “Differential current switch logic: a low power DCVS logic family,” in IEEE Journal of Solid-State Circuits, Vol. 31, pp. 981 —991, 1996.
[29] Y.K. Tan and Y.C. Lim “Self-timed precharge Latch,” in Int’l Symp. Circuits and Systems, Vol. 1, pp. 566 —569, 1990.
[30] Shyh-Jye Jou and I-Yao Chuang, “Low-power globally asynchronous locally synchronous design using self-timed circuit technology,” in Proc. Int’l Symp. Circuits and Systems , Vol. 3 , pp. 1808 —1811, 1997.
[31] L. Benini, P. Siegel, and G. De Micheli, “Saving power by synthesizing gated clocks for sequential circuits,” in IEEE Design & Test of Computers , Vol. 11, pp. 32 —41, Winter 1994.
[32] N. Bellas, I.N. Hajj, C.D. Polychronopoulos, and G. Stamoulis, “Architectural and compiler techniques for energy reduction in high-performance microprocessors,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 8, pp. 317-326, June 2000.