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研究生:王瑛嘉
論文名稱:低功率結構式預先計算邏輯合成設計
論文名稱(外文):Structural precomputation design for low-power logic synthesis
指導教授:王行健
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:51
中文關鍵詞:預先計算低功率電力消耗
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功率消耗在傳統的VLSI晶片設計上是一個被忽略的課題。因為在過去無論是晶片的複雜度或是系統運作的頻率都是非常的低,低到讓我們根本不需要考慮這一個問題。
超大型積體電路在最近幾年裡,因為製程技術不斷提昇、快速的操作頻率、百萬的電晶體做於單一晶片上,低功率消耗已成為一件不可避免而且艱鉅的挑戰。由於低功率應用的需求日益增加使這個問題更加複雜,如筆記型電腦,醫療器材,通訊產品和符合環保要求的桌上型電腦,這些應用都需要降低整體的功率消耗。所以除了操作頻率外,對今日的積體電路設計者而言,功率消耗已經變成了一個非常重要設計的考慮因素。
在這一論文中,我們藉由邏輯結構的分析,找出最好的CUBE,來做預先計算,以控制輸入暫存器的工作。實驗結果顯示,有許多個電路可以逹到減少60%以上,而平均的功率消耗可以減少50.17%。

Power dissipation of VLSI chip is traditionally a neglected subject. In the past, the device density and operating frequency were low enough that it was not a constraining factor in the chips.
As the VLSI process technology continuously improves in recent years, low power consumption has become increasingly important in hand-held communication systems and battery operated equipment, such as laptop computers, multimedia products and cellular phones. In addition to performance, power is becoming a significant concern for designers.
In the thesis, we try to find out the best precomputation logic from a circuit by calculating a power-saving metric, which is determined from the logic analysis of the circuit’s information. As a result, the power reductions achieved by our approach are drastic over 60% for some circuits. We obtain average power reductions of 50.17%.

誌謝 1
Abstract 2
摘要 3
目錄 4
圖 6
表 6
第一章 簡介 7
第一節 問題描述 7
第二節 研究動機與目標 8
第三節 軟體功能及特性 8
第四節 貢獻及成果簡述 9
第五節 內容大綱 9
第二章 背景知識與相關研究 10
第一節 功率消耗的元素和功率消耗模型 10
(一) 轉換或電容功率 11
(二) 內部或短路功率 11
(三) 漏電或靜態功率 11
第二節 轉換次數導致的功率消耗 12
第三節 功率消耗的評估 12
第四節 邏輯合成流程 13
第五節 相關研究 14
第三章 系統架構分析 16
第一節 架構一 16
第二節 架構二 17
第三節 架構三 18
第四節 例子 18
第四章 實作 21
第一節 輸入檔案格式 21
第二節 資料結構 22
第三節 程式流程 22
第五章 演算法 24
第一節 方法一 ON-Set Cube 24
第二節 方法二 OFF-Set Cube 26
第三節 方法三 單互補性 27
第四節 方法四 雙互補性 32
第五節 方法五 相依性 35
第六節 方法六 Cube交集 38
第六章 實驗結果 42
第一節 工作平台及程式語言 42
第二節 結果分析 42
第七章 結論與未來工作 45
參考文獻 46
附錄:使用手冊 51
A. 如何編譯程式 51
B. 如何執行程式 51

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