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研究生:陳勁興
論文名稱:較少的完全自我檢查電路硬體需求應用在有限狀態機輸出使用BergerCode
論文名稱(外文):Lower Hardware Redundancy TSC For Finite State Machine Output Using Berger Code
指導教授:王行健
學位類別:碩士
校院名稱:國立中興大學
系所名稱:資訊科學研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
中文關鍵詞:完全自我檢查Berger Code
相關次數:
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使用Berger code的編碼方式來設計一個完全自我檢查有限狀態機,主要的缺點是所需要的硬體消耗(Hardware overhead)較其他的編碼方式(如:m-out-of-n code)大。
本篇論文提出將有限狀態機的輸出位元經過適當的合併後以較少的位元使用Berger code編碼同時不改變Berger code的編碼結構,以便減少Berger code與完全自我檢查(Totally self-checking)主要的缺點,亦即在產生檢查碼時檢查碼產生器(Check Bit Generator)與驗證有限狀態機電路正確性的雙軌檢查器(Two-rail checker)所需較多的硬體消耗目的。
然而在選取適當的可合併輸出位元過程中發現亦屬於演算法理論內的派系分割的問題(Clique Partition),這個問題將使得無法在多項式時間(Polynomial Time)找出解。

目錄
第一章 簡介……………………………………………………………1
1.1 研究動機……………………………………………………...2
1.2 研究目標……………………………………………………...3
第二章 背景知識………………………………………………………4
2.1 自我檢查(Self-checking)…………………………………5
2.2 完全自我檢查檢查器………………………………………..7
2.3 雙軌檢查器(Two-rail checker)……………………………8
2.4 Berger code…………………………………………………..10
2.5 完全自我檢查檢查器使用Berger code…………………….12
2.6 檢查碼產生器使用Berger code…………………………….13
2.7 完全自我檢查有限狀態機……….…………………………14
2.8 最小派系分割(Minimum Clique Partition)…………………16
第三章 合併有限狀態機輸出位元……….………………………….17
3.1 合併電路所需XOR邏輯閘計算方式………………………25
第四章 實驗分析結果………………………………………………..26
4.1 所需檢查碼產生器與合併電路的硬體消耗……………….28
4.2 所需雙軌檢查器的硬體消耗……………………………….31
4.3 有限狀態機輸出經合併後對電路錯誤涵蓋率之影響……32
4.4 提高有限狀態機外加合併電路的錯誤涵蓋率……………35
第五章 結論與未來研究工作……………………………………….38
參考文獻……………………………………………………………….40

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