# 臺灣博碩士論文加值系統

(54.161.24.9) 您好！臺灣時間：2022/01/17 12:45

:::

### 詳目顯示

:

• 被引用:0
• 點閱:1094
• 評分:
• 下載:127
• 書目收藏:0
 這篇論文著眼於電路運作中的同步錯誤偵測的研究。我們的想法是利用加法或減法的運算，使得輸出的個數可以用每次減半的速度遞減，反覆進行同樣的步驟，一直到產生出我們需要的檢查位元個數為止。
 第一章 簡介…………………………………………………1 1.1 研究動機……………………………………………1 1.2 內容大綱……………………………………………4 第二章 背景知識……………………………………………5 2.1 同步錯誤偵測………………………………………5 2.2 完全自我檢查電路……………………..…………6 2.3 檢查器…………………………………..…………6 2.4 錯誤類型和漢明距離………………………………8 2.5 錯誤偵測碼………………………………………..9 第三章 同步錯誤偵測架構………………………………….12 3.1 基本架構…………………………………………………12 3.2 基本分析…………………………………………………14 第四章 實驗……………………………………….………23 4.1 實驗步驟………………………………………….23 4.2 實驗結果……………………………………….…25 第五章 結論與未來工作……………………………….…31 參考文獻…………………………………………..…………32
 [1] Nicolaidis, M., “On-line Testing for VLSI: State of the Art and Techniques,” Integration, the VLSI Journal, Vol. 26, No. 1-2, pp. 197-209, Dec. 1998.[2] De, K., C. Natarajan, D. Nair, and P. Banerjee, “RSYN: A System for Automated Synthesis of Reliable Multilevel Circuits,” IEEE Trans. VLSI Systems, pp. 186-195, Jun. 1994.[3] Saposhnikov, V. V., A. Morosov, VL. V. Saposhnikov, and M. Gössel, “A New Design Method for Self-Checking Unidirectional Combinational Circuits,” Journal of Electronic Testing: Theory and Applications, pp. 41-53, 1998.[4] Touba, N.A., and E.J. McCluskey, “"Logic Synthesis of Multilevel Circuits with Concurrent Error Detection", IEEE Transactions on Computer-Aided Design, Vol. 16, No. 7, pp. 783-789, Jul. 1997.[5] Das, D., and N. A. Touba, “Synthesis of Low-Cost Concurrent Error Detection Based on Bose-Lin Codes,” Proc. Of VLSI Test Symposium, pp. 309-315, 1998.[6] Das, D., and N. A. Touba, “Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits”, Proc. of VLSI Test Symposium, pp. 370-376, 1999.[7] Anderson, D. A., “Design of Self-Checking Digital Network, Using Coding Techniques,” Coordinated Sci. Lab. Univ. Illinois, Urbana-Champaign, Rep R-527,June 1984.[8] Anderson, D. A., “Design of Self-Checking Digital Network, Using Coding Techniques,” Univ. Illinois,CSL Report R-527,September,1972.[9] J. M. Berger, “A note on error detection codes for asymmetric binary channels”, Inform. Contr., pp 68-73 , Mar. 1961.[10] M. Marouf and A. D. Friedman, “Design of Self-Checking Checkers for Berger Codes,” Digest of Papers 8th Annual Intn’l. Conf. On Fault-Tolerant Computing, pp. 179-184, June, 1978.[11] Gorshe, S., and B. Bose, “A Self-Checking ALU Design with Efficient Codes,” Proc. of VLSI Test Symposium, pp. 157-161, 1996.[12] Jha, N.K., and S.Wang, “Design and Synthesis of Self-Checking VLSI Circuits,” IEEE Trans. Computer-Aided Design, Vol. 12, No.6, pp. 878-887, Jun. 1993.[13] Kavousianos, X., and D. Nikolos, “Self-Exercising, Self-Testing k-order Comparators,” Proc. Of VLSI Test Symposium, pp. 216-221, 1997.[14] Kavousianos, X., and D. Nikolos, “Novel single and Double Output TSC Berger Code Checkers,” Proc. of VLSI Test Symposium, pp. 348-353, 1998.[15] Lo, J.-C., S. Thanawastein, and M. Nicolaidis, “An SFS Berger Check Prediction ALU and Its Application to Self-Checking Processor Designs,” IEEE Trans. on Computer Aided-Design, Vol. 11, No. 4, pp. 525-540, Apr. 1992.[16] Mak, G.P, J.A. Abraham, and E.S. Davidson, “The Design of PLAs with Concurrent Error Detection,” Proc. FTCS, pp. 303-310, Jun. 1982.[17] Nicolaidis, M., and M. Boudjit, “New Implmentations, Tools, and Experiments for Decreasing Self-Checking PLAs Area Overhead,” Proc. of International Conference on Computer Design, pp. 275-281, 1991.[18] Goessel, M., and S. Graf, Error Detection Circuits, London, NY: McGraw-Hill, 1993.[19] Pradhan, D.K., Fault Tolerant Computing: Theory and Techniques, Vol. 1, Englewood Cliffs, NJ: Prentice-Hall, 1986, Chap. 5.[20] Touba, N.A., and E.J. McCluskey, “Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection,” International Conf. Computer-Aided Design, pp. 651-654, 1994.[21] Anderson, D. A., “Design of Self-Checking Saxena N.R., and J.P. Robinson, “Accumulator compression testing,” IEEE Transactions on Computers, vol.C-35, no.4, pp. 317-21, April 1986.[22] Anderson, D.A., “Design of Self-Checking Digital Networks Using Coding Techniques," Technical Report R-527, Coordinated Science Laboratory, University of Illinois, Urbana, IL, 1971.[23] Bose, B., and D.J. Lin, “Systematic Unidirectional Error-Detecting Codes,” IEEE Trans. on Computer Aided-Design, Vol. C-34, No. 11, pp. 1024-1032, Nov. 1985.[24] Brayton, R.K., R. Rudell, A. Sangiovanni-Vincentelli, and A.R. Wang, “MIS: A Multiple-Level Logic Optimization System,” IEEE Trans. on Computer Aided-Design, Vol. 6, pp. 1062-1081, Nov. 1987.[25] Detjens, E., G. Gannot, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, “Technology Mapping in MIS,” Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 1987, pp. 116-119.[26] Devadas, S., Ma, Hi-Keung, Newton, A.R., and A. Sangiovanni- Vincentelli, “MUSTANG: State Assignment of Finite State Machines Targeting Multilevel Logic Implementations,” IEEE Trans. on Computer Aided-Design, Vol. 7, No. 12, pp. 1290-1299, Dec. 1988.[27] Gupta, S.K., and D.K. Pradhan, “Can Concurrent Checkers help BIST?,” Proc. IEEE Int. Test Conf., 1992,pp. 140-150
 電子全文
 國圖紙本論文
 推文當script無法執行時可按︰推文 網路書籤當script無法執行時可按︰網路書籤 推薦當script無法執行時可按︰推薦 評分當script無法執行時可按︰評分 引用網址當script無法執行時可按︰引用網址 轉寄當script無法執行時可按︰轉寄

 無相關論文

 無相關期刊

 1 一個改變向量種子的技術應用於以線性回饋移位暫存器為基礎的內建式自我測試 2 利用分段法改善線性規劃式無線廣播機制 3 較少的完全自我檢查電路硬體需求應用在有限狀態機輸出使用BergerCode 4 關於線性回饋移位暫存器特徵多項式之選擇的研究 5 特有植物臺灣粗榧保育之研究：以族群遺傳變異及生態生理特性之觀點 6 低功率結構式預先計算邏輯合成設計 7 一個結合離散小波轉換與人類視覺特性之數位浮水印技術 8 可恢復訊息之公平盲簽章方法之探討 9 應用影像處理與基因演算法於視覺密碼學之研究 10 應用ISSR研究玉山圓柏之遺傳變異 11 利用不可分割簽章法保護行動代理人之研究 12 利用鍵值和存取頻率改善調整時間之樹狀廣播結構 13 消費者特性與網際網路購物意願關係之研究--以生鮮食品為例 14 購買涉入、購買動機、網站環境特性對網路生鮮蔬菜購買意願之影響

 簡易查詢 | 進階查詢 | 熱門排行 | 我的研究室