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研究生:梁雅惠 
研究生(外文):Ya-Hui Liang
論文名稱:應用在藍芽之頻率合成器
論文名稱(外文):A Frequency Synthesizer for Bluetooth Applications
指導教授:張振豪
指導教授(外文):Robert C. Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:藍芽科技頻率合成器可程式化除頻器壓控振盪器相頻偵測器頻率選擇雙模預除頻器2.4GHz
外文關鍵詞:Bluetooth2.4GHzphase-frequency detector (PFD)VCOprogrammable frequency dividerdual-modulus prescalerprogrammable swallow counterchannel selection
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摘 要
本篇論文描述一個應用於2.4GHz藍芽科技上的頻率合成器。它包含相頻偵測器,電荷充放式電路,迴路濾波器,壓控振盪器,以及可程式化除頻器。此頻率合成器,可被運用在無線通訊系統中,提供本地振盪器的載波訊號。
而在此研究中,我們使用整數N的頻率合成器應用於藍芽科技上。相頻偵測器用來偵測外部參考信號與內部除頻後的信號間的相位及頻率差。而迴路濾波器則可抑制高頻的雜訊。壓控振盪器採用環形振盪器的架構。由CMOS拴鎖式差動對組成內部延遲單元,接受控制電壓調變延遲單元的延遲時間,以調變輸出的頻率。應用可程式化除頻器,來達到頻率選擇。可程式化除頻器主要由一雙模預除頻器,固定除數的計數器,及一可程式化的餘數除頻器組成。
此頻率合成器使用TSMC 0.35μm CMOS 1P4M的製程技術,模擬與製作。整個晶片的面積為870μm ×650μm,消耗功率是60mW。

Abstract
This thesis describes a frequency synthesizer for 2.4GHz Bluetooth applications. It is composed of a phase-frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a programmable frequency divider. This frequency synthesizer can be employed in the wireless communication system to generate carrier signals for local oscillator.
In this work, we used an integer-N frequency synthesizer for Bluetooth applications. The PFD detects the phase and frequency difference between reference input and programmable frequency divider output. The loop filter can suppress noise at high frequency. The VCO adopts the ring oscillator structure. The delay time of the delay cell, which is composed of a CMOS latch differential-pair, can be changed by the control voltage. The programmable frequency divider can facilitate channel selection. It consists of a dual-modulus prescaler, a fixed-ratio program counter, and a programmable swallow counter.
This frequency synthesizer is simulated and implemented by TSMC 0.35μm CMOS 1P4M technology. The total chip area is 870μm × 650μm. The power consumption is 60mW.

Contents
ABSTRACT (CHINESE) Ⅰ
ABSTRACT (ENGLISH) Ⅱ
ACKNOWLEDGEMENT Ⅲ
CONTENTS Ⅳ
LIST OF FIGURES Ⅶ
LIST OF TABLES Ⅹ
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Bluetooth Overview 2
1.3 Thesis Organization 3
Chapter 2 PLL Frequency Synthesizer 4
2.1 Introduction 4
2.2 PLL Fundamentals 5
2.2.1 Noise Characteristic 8
2.2.2 Reference Spurs 9
2.3 Higher-order PLL Design 12
2.3.1 Second-order PLL 12
2.3.2 Third-order PLL 15
2.4 PLL Applications 18
2.4.1 Jitter and Skew Suppression 18
2.4.2 Clock Recovery 19
2.4.3 Frequency Synthesis 19
2.5 RF Synthesizer Architectures 19
2.5.1 Integer-N Architecture 20
2.5.2 Fractional-N Architecture 22
Chapter 3 Design of PFD, Charge Pump, and Loop Filter 25
3.1 Basic Operations of PFD and Charge Pump 25
3.2 Implementation of PFD 28
3.3 Implementation of Charge Pump 30
3.4 Loop Filter 33
3.4.1 Second-order Loop Filter 33
3.4.2 Third-order Loop Filter 36
3.4.3 Design of Second-order Loop Filter 38
Chapter 4 Voltage Controlled Oscillator 39
4.1 General Considerations 39
4.2 LC Oscillators 43
4.3 Ring Oscillator 47
4.3.1 Fundamental of Ring Oscillator 47
4.3.2 Implementation of Ring Oscillator 48
Chapter 5 Synthesizer Design 53
5.1 Synthesizer Architecture 53
5.2 Design of Pulse Swallow Counter 54
5.3 Dual Modulus Prescaler 55
5.3.1 Divide-by-4/5 Circuit 55
5.3.2 Divide-by-two Circuit 58
5.3.3 Divide-by-16/17 Prescaler 59
5.4 Swallow Counter 59
5.5 Summary of Frequency Synthesizer 61
Chapter 6 Conclusions 64
References 65

References
[1] http://www.stanford.edu/~rapaport/new_page_1.htm
[2] http://www.dell.com/us/en/ipd/topics/vectors_1999~blue.htm
[3] Dale G. Wilson, Woogeun Rhee, and Bang-Sup Song, “Integrated RF receiver front ends and frequency synthesizers for wireless.” Designing Low Power Digital Systems, Emerging Technologies, pp.269-272, 1996.
[4] Behzad Razavi, RF Microelectronics, Prentice Hall, Inc., 1998.
[5] Dean Banerjee, “PLL performance, simulation, and design,” Copyright 1998 National Semiconductor.
[6] J. Craninckx and M. Steyaert, Wireless CMOS Frequency Synthesizer Design, Kluwer Academic Publishers, Boston, 1998.
[7] Behzad Razavi, Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design, the Institute of Electrical and Electronics Engineers, Inc., 1996.
[8] T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewsky, “Sigma-delta modulation in fractional-N frequency synthesis,” IEEE of Solid-State Circuits, Vol. 28, pp. 553-559, May 1993.
[9] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[10] Won-Hyo Lee, Jun-Dong Cho, Sung-Dae Lee, “A high speed and low power phase-frequency detector and charge-pump,” Design Automation Conference, 1999. Proceedings of the ASP-DAC ’99, Vo1.1, pp. 269-272, 1999.
[11] W. O. Keese, "An analysis and performance evaluation of a passive filter design technique for charge pump phase-locked loops," National Semiconductor Application Note, no. 1001, May 1996.
[12] N. M. Nguyen and R. G. Meyer, "Start-up and frequency stability in high-frequency oscillators," IEEE J. of Solid-State Circuits, vol.27, pp. 810-820, May 1992.
[13] Chan-Hong Park, Beomsup Kim, “A Low-Noise, 900-MHz VCO in 0.6-um CMOS,” IEEE J. of Solid-State Circuits, vol.34, May 1999.
[14] S. J. Lee, B. Kim, and K. Lee, “A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme,” IEEE J. of Solid-State Circuits, vol. 32, pp. 289-291, Feb. 1997.
[15] Tai-Cheng Lee and Behzad Razavi, “A stabilization technique for phase-locked frequency synthesizers,” Sym.On VLSI Circuits Dig. Tech. Paper,pp. 39-42, 2001.
[16] C. Lam and B. Razavi, “A 2.6GHz/5.2GHz frequency synthesizer in 0.4um CMOS technology,” IEEE J. Solid-state Circuits, vol. 35, pp. 788-794, May 2000.
[17] J. Yuan and C. Svensson, "High speed CMOS circuit technique," IEEE J. of Solid-State Circuits, vol.24, pp. 62-70, February 1989.
[18] C. Y. Yang et al., "New dynamic flip-flops for high-speed dual-modulus prescaler," IEEE J. of Solid-State Circuits, vol.33, pp. 1568-1571, October 1998.
[19] R. Rogenmoser et al., “1.57 GHz asynchronous and 1.4 GHz dual-modulus 1.2-mm CMOS prescalers,” Proc. CICC, pp. 387—390, 1994.

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