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研究生:林心蕾 
研究生(外文):Hsin-Lei Lin
論文名稱:IEEE802.11b無線區域網路系統之決策迴授等化器設計
論文名稱(外文):Design of a Decision Feedback Equalizer for IEEE 802.11b WLAN System
指導教授:張振豪
指導教授(外文):Robert C. Chang
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
中文關鍵詞:決策迴授等化器
外文關鍵詞:decision feedbaack equalizer
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本篇論文中,將介紹一個以IEEE 802.11b協定為基礎之決策迴授等化器設計。此等化器之濾波器部分,以雙重6個分接頭(dual 6-tap)的前置濾波器及雙重8個分接頭(dual 8-tap)迴授濾波器組成,輸入資料之位元數分別為6位元及2位元,而其架構乃由有限個數之脈衝響應濾波器(FIR)實現。等化器的輸出信號則是依據後端互補碼調變(CCK)之需求,而利用決策器將訊號切成兩個層次。最小均方(LMS)演算法估測通道,以對此平行架構之決策迴授等化器在其係數做更新。在TSMC 0.35 m CMOS 1p4m技術下,所模擬的最長路徑消耗時間為19.46 nsec。總面積為58624個閘數目。操作在3.3V的供應電壓下之功率消耗為25.087 mW。

In this thesis, design of a decision feedback equalizer (DFE) based on IEEE 802.11b protocol is presented. It has dual 6-tap feed-forward filters with 6-bit input and an 8-tap feedback filter with 2-bit input, that all the filters are implemented using the finite impulse response (FIR) filter. The output of the DFE is sliced into two levels by detector for CCK (8-chip complementary code keying) modulation. The least mean square (LMS) algorithm is used for updating the coefficients in the parallel DFE architecture. The data elapse time in the critical path is 19.46 nsec. The DFE is implemented using the TSMC 0.35 m CMOS 1p4m technology. The total gate count is 58624. The power consumption is 25.087 mW operating under a 3.3 V supply voltage.

Contents
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Organization of this Thesis 1
Chapter 2 The WLAN System 3
2.1 Environment 3
2.2 Basic Technology of the WLAN System 7
2.2.1 Direct Sequence Spread Spectrum PHY technique 7
2.2.2 High Rate Technique 8
2.3 Architecture of the Transmitter 10
2.4 Channel Model 12
2.5 Architecture of the Receiver 15
Chapter 3 Algorithm of the Equalizer 19
3.1 Linear Equalizer 21
3.2 Non-linear Equalizer 23
3.3 Adaptive Filtering Algorithm 25
3.3.1 Least-Mean-Square (LMS) Algorithm 25
3.3.2 Recursive Least-Squares (RLS) Estimation 27
3.3.3 Decision of the Adaptive Filtering Algorithm 28
3.4 Adaptive Decision Feedback Equalizer 29
3.4.1 Adaptive Equalizer 29
3.4.2 Adaptive Decision Feedback Equalizer 31
3.5 High-Level Simulation Results 34
Chapter 4 Analysis and Design of DFE Architecture 37
4.1 Introduction 37
4.2 Hardware Cost of the Architecture 38
4.3 Building Blocks of the DFE 42
4.3.1 Filter 42
4.3.1.1 Selection of FIR Filter Structure 42
4.3.1.2 Feed-forward Filter 44
4.3.1.3 Feedback Filter 45
4.3.2 Coefficient Update Block 46
4.3.3 Detector 48
Chapter 5 Implementation of the Decision Feedback Equalizer 51
5.1 Specification of the Decision Feedback Equalizer 51
5.2 Architecture of the Decision Feedback Equalizer 54
5.3 RTL-Level Simulation 55
5.3.1 Behavior Models 56
5.3.2 Verification Strategy 57
5.3.2.1 Signal Level 57
5.3.2.2 System Level 57
5.3.3 Test Plan/Methods and Testability Measure 58
5.3.3.1 Generating the Text Bench 58
5.3.3.2 Method of Testing 59
5.4 Logic-Level Simulation 63
Chapter 6 Conclusion 67
Reference 68

Reference
[1] IEEE Std 802.11b, September 1999, ISBN 0-7381-1811-7.
[2] Kaveh Pahlavan and Allen H. Levesque, Wireless Information Networks, Jonn Wiley & Sons, 1995, ISBN 0-471-10607-0.
[3] Abdulkareem B. Adinoyi, Saud A. Al-Semari, and Azzedine Zerguine, “Performance of equalized I-Q QPSK over 2-ray rayleigh fading,” Conference on Signals, Systems, and Computers, vol.1, pp.306 —309, 1999
[4] Gregory M. Durant and Sirikiat Ariyavisitakul,“Implementation of a broadband equalizer for high-speed wireless data applications,” IEEE 1998 International Conference on Universal Personal Communications, vol.2, pp. 1015 —1020, 1998.
[5] 黃能富, “區域網路與高速網路,”維科出版社, Jun.1998, ISBN 957-86-7540-2.
[6] S. M. Bozic, Digital and Kalman Filtering second edition, Great Britain for Edward Arnold, 1994, ISBN 0-340-61057-3.
[7] Simon Haykin, Adaptive Filter Theory, Prentice-Hall, 1996, ISBN 0-13-322760-X.
[8] Tai-Kuo Woo, “HRLS: a more efficient RLS algorithm for adaptive FIR filtering,” IEEE Communications Letters, vol. 5, iss.3, pp.81-84 , March 2001.
[9] M.M. Aly; K. Sharaf, H.F. Ragai, “On the utilization of strength-reduced architectures for adaptive equalizers,” IEEE International Symposium on Circuits and Systems, vol.3, pp.287 —290, 2000.
[10] Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun Dong Cho, Jea Woo Kim, Jae Kon Lee, Hyeon Cheol Park, and Ki Won Lee, “Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modem”, Design Automation Conference in Asia and South Pacific, pp.404-407, 2001.
[11] Peijun Shan and Eric J. King, “Cancel multipath interference in spread-spectrum communications,” Wireless Systems Design, March 2001.
[12] Pei-Lung Lin, Jinn-Shyan Wang, “A low-cost high-symbol-rate equalizer chip for HIPERLAN system,” MA. Thesis, Dept. of Electrical Engineering, National Chung Cheng University, Taiwan, R.O.C., August 1999.
[13] Gregory T. Uehara, Caesar S. H. Wong, Jacques C. Rudell, and Paul R. Gray, “A 50 MHz 70 mW 8-tap adaptive equalizer/Viterbi sequence detector in 1.2 m CMOS,” IEEE Custom Integrated Circuits Conference, pp. 51 —54, 1994.
[14] Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun Dong Cho, Jea Woo Kim, Jae Kon Lee, Hyeon Cheol Park, Ki Won Lee, “Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modem,” Asia and South Pacific Design Automation Conference, pp. 404 -407, 2001.

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