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研究生:邱韋達 
論文名稱:高速類比數位轉換器之設計
論文名稱(外文):Design of High-Speed CMOS Flash Analog-to-Digital Converter
指導教授:張振豪
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:法文
論文頁數:51
中文關鍵詞:快閃式類比數位轉換器比較器前置放大器取樣保持電路
外文關鍵詞:flashADCcomparatorpreamplifierS/H
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類比數位轉換技術是現今積體電路中不可忽視的一環,特別是在資料的傳輸,一個快速精確的A/D轉換器將可大大的減少前級和數位電路的規格要求,本論文中利用差動快閃式的架構設計一個6位元、取樣頻率為500MHz以上的類比數位轉換器,可偵測最小電壓差為20毫伏。為了完成高速和正確的要求,我們使用了分佈式的取樣保持電路、前置放大器和平均的技巧來改善非線性因素對於電路的影響,電位解碼電路來抑制錯誤的發生。此快閃式類比數位轉換器的實現是利用台積電CMOS 0.35μm、1P4M製程來設計,由HSPICE的模擬結果顯示,整個電路在3.3V的電源供應及833MHz的取樣頻率下,有著700mW的功率消耗

The analog-to-digital conversion technique plays an important role in recent develop of integrated circuits, especially in data transmission circuits. A high-speed and precise A/D converter in systems can decrease the required specifications of the front-end and digital portion. This thesis describes the design of a 6-bit, differential and over 500MHz sampling rate A/D converter, which can sense 20mV voltage difference. In order to achieve high-speed and precise objective, we used the distributed S/H, preamplfier and the average technique to improve the relative non-linearity. In addition, the digital encoder is used to suppress the error rate. The flash A/D converter is designed using the in TSMC 0.35μm, 1P4M CMOS technology. HSPICE simulation results show that the A/D converter dissipates 700mW at 833MHz of sampling rate with 3.3V power supply.

Contents
摘 要 i
Abstract ii
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Partial Response Maximum Likelihood 2
1.3 Organization 4
Chapter 2 Architectures of High-speed A/D Converters 5
2.1 Flash Converter Architecture 5
2.2 Interpolating A/D Converter Architecture 7
2.3 Folding A/D Converter Architecture 8
2.4 Two-step A/D Converter Architecture 10
2.5 Pipeline A/D Converter Architecture 11
2.6 Time-Interleaved A/D Converter Architecture 13
Chapter 3 Design and Analysis of Flash A/D 15
3.1 System Structure 15
3.2 Reference Resistor 15
3.3 Sample-and-Hold 17
3.4 Preamplifier 21
3.5 Dummy Component 25
3.6 Comparator 26
3.7 Average Resistor Network 30
3.8 D-FFs in TSPC 31
3.9 Encoder 33
Chapter 4 Testing of A/D Converter 39
4.1 A/D Specifications 39
4.1.1 Resolution and Dynamic Range 39
4.1.2 Nonlinearity 40
4.1.3 Signal to Noise Ratio (SNR) 41
4.1.4 Signal to Noise plus Distortion Ratio (SNDR) 41
4.2 Code Density Testing Theory 42
4.3 The Frequency Domain Analysis 44
Chapter 5 Conclusions 50
Reference 52

Reference
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