在本論文中我們主要討論頻率及相位漂移對IEEE 802.11b基頻接收機所造成的影響，在IEEE所制定的IEEE 802.11b協定中規定它的中心頻率是在2.4GHz這個頻段，而它可容許的頻率偏差是+/- 25 ppm，所以我們可以知道這整個系統可以容許的頻率偏差範圍是+/- 120 KHz，因此我們採用載波回復電路來移除介於傳輸信號及接收信號之的頻率偏差，並修正所接收到信號的相位錯誤

In this thesis, we describes the frequency offset and phase offset effects of IEEE 802.11b BBP receiver. The standard specifies that its central frequency is in the 2.4GHz bands, and the frequency offset tolerance is +/- 25 ppm. Therefore, the whole system has +/- 120 KHz frequency tolerance. Here, we use a carrier recovery loop circuit to remove the frequency offset between transmitter and receiver and to correct the phase offset of the received signal.

摘 要 i
ABSTRACT ii
誌 謝 iii
Contents iv
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Thesis Organization 2
Chapter 2 Overview of High-Speed Wireless LAN 3
2.1 Introduction to Wireless Communication Systems 3
2.2 The IEEE 802.11b WLAN 5
2.2.1 Introduction 5
2.2.2 High Rate PHY Layer and PPDU Format 7
2.3 Spread Spectrum Technology and Modulation 10
2.3.1 Direct Sequences Spread Spectrum 10
2.3.2 Differential Binary Phase Shift Keying 12
2.3.3 Differential Quadrature Phase Shift Keying 13
2.3.4 Barker Sequences 15
2.3.5 Complementary Coke Keying 16
2.4 IEEE 802.11b Baseband Processor 18
2.4.1 Block Diagram of BBP Transmitter 19
2.4.2 Block Diagram of BBP Receiver 20
Chapter 3 Carrier Recovery Loop 22
3.1 Introduction to Carrier Recovery 22
3.2 Phase-Locked Loops 23
3.2.1 PLL Analysis 23
3.2.2 Costas Loop 31
3.2.3 Modified Costas Loop 33
3.3 De-rotator 34
3.4 Theorem of the Phase Detector 36
3.4.1 Maximum Likelihood Estimation 38
3.4.2 Cross Product Detector 39
3.4.3 Modified Costas Detector 40
3.5 Loop Filter 44
3.6 NCO 46
3.6.1 Rom-based NCO 48
3.6.2 Rom-less NCO 49
Chapter 4 Hardware Implementation 52
4.1 Cell-based Design Flow 52
4.2 Simulation Results 53
4.2.1 MATLAB Simulation Results 54
4.2.2 RTL Simulation Results 57
4.2.3 Logic-Level Simulation Results 64
4.3 Physical Layout and Chip Summary 66
Chapter 5 Conclusions 68
Reference 69

[1] 黃能富，區域網路與高速網路，維科出版社，1998
[2] Intersil, HFA3863 Data sheet, Apr,2000.
[3] IEEE 802.11b standard, Sep,1999.
[4] Simon Haykin, Communication System, third edition, New York: John Wiley & sons, 1994.
[5] K. Feher, Digital communication: Statellite/Earth station Engineering Englewood Cliffs, NJ: Prentice-Hall, 1983.
[6] Heinrich Meyr and Gerf Ascheid, Synchronization in Digital Communications, Volume 1:Phase-, Frequency-Locked Loops, and Amplitude Control, New York:John Wiley & Sons, 1990.
[7] John G. Proakies, Digital Communication, Fourth edition, McGraw-Hill, 2001.
[8] W. C. Lindesy and M. K. Simon, Telecommunications System Engineering, Englewood Cliffs, NJ: Prentice-Hall, 1973.
[9] John A. Bingham, The Theory and Practice of Modem Design, New York: John Wiley & Sons, 1988.
[10] Edward A. Lee and David G. Messerschmitt, Digital Communication, second edition, Boston: Kluwer Academic Publishers, 1994.
[11] R. E. Ziemer and W.h. Tranter, Principles of Communications, Houghton Mifflin, Boston 1995.
[12] Francis D. Natali, “AFC Tracking Algorithms”, IEEE Trans. On communication, vol. COM-32, no.8 pp.935-947, August, 1984.
[13] Roland E. Best, Phase-Locked Loops: Design, Simulation, and Applications, Fourth Edition, McGraw-Hill, New York, 1999.
[14] F. M. Gardner, Phaselock Techniques, second edition, Wiley-Interscience,1979.
[15] Jack Kurzweil, An introduction to digital communications, Wiley, New York, 2000.
[16] J. K. Holmes, Digital Communication, Wiley, New York, 1982.
[17] B.Y. Chung, C. Chien, H. Samueli, and R. Jain, “Performance analysis of an All-Digital BPSK Direct-Sequence Spread-Spectrum IF Receiver Architecture,”IEEE Journal on Selected Areas in Communication, vol. 11,no. 7, pp.1096-1107, Sep. 1993.
[18] A. Madisetti, A. Y. Kwentus, “ A100MHz, 16-b, direct digital frequency synthesizer with a 100dBc spurious-free dynamic range,”IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1034-1043, Aug. 1999.
[19] Mortezapour, S., Lee, E.K.F.,”Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter,”IEEE J. Solid-State Circuits, vol. 34, pp. 1350-1359, Oct. 1999.
[20] Amir M. Sodagar, G. R. Lahji,”Mapping from phase to sine-amplitude in direct digital frequency synthesizers using parabolic approximation,”IEEE Trans. On Circuit and Systems II: Analog and Digital signal processing, vol.47, no.12, Dec. 2000.
[21] Kalle I. Palomaki, Jarkko Nittylahti, “Direct digital frequency synthesizer architecture based on Chebyshev approximation,” Signals, Systems and Computers, 2000. Conference Record of the Thirty-Fourth Asilomar Conference on , Vol.2, pp. 1639-1643, 2000 .