跳到主要內容

臺灣博碩士論文加值系統

(75.101.211.110) 您好!臺灣時間:2022/01/26 12:50
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:黃志豪 
論文名稱:應用於無線區域網路IEEE802.11b之互補碼解調變、時序回復與Rake之設計與製作
論文名稱(外文):Design and Implementation of CCK Demodulator、Timing Recovery and Rake for Wireless LAN IEEE 802.11b
指導教授:林泓均
學位類別:碩士
校院名稱:國立中興大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:77
中文關鍵詞:無線區域網路IEEE 802.11b互補碼解調變時序回復Rake
外文關鍵詞:Wireless LANIEEE 802.11bCCK DemodulatorTiming RecoveryRake
相關次數:
  • 被引用被引用:0
  • 點閱點閱:437
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來隨著科技的進步,資料的傳輸方式,已由有線通訊傳輸,進入無線通訊領域,許多無線通訊系統路陸續被提出,無線區域網路IEEE 802.11便是其中之一。IEEE 802.11剛提出時,其資料傳輸速率為1Mbps與2Mbps,由於無線通訊系統以進入多媒體傳送,1Mbps與2Mbps以不能滿足所需,無線區域網路另一傳輸系統被提出,稱之IEEE 802.11b,其資料傳輸速率為5.5Mbps與11Mbps。由於IEEE 802.11b系統資料傳輸速率的提高,相對地,通道中雜訊、干擾與多路徑等效應將變的相當明顯,導致訊號不易辯識,訊雜比因此降低。
本論文研究方向為探討如何設計無線區域網路IEEE 802.11b之接收端基頻電路,借由Matlab與Verilog的模擬,設計時序回復與信號同步電路、提高訊雜比之RAKE電路、硬體需求低之新型互補碼解調變電路。
時序回復與信號同步電路主導接收端資料正確運作,藉由巴克碼的完美相關性,決定時序回復時脈,進而延申出其它電路方快所需之時脈。RAKE電路由通道估測器與通道匹配濾波器構成,藉由通道估測器估測通道多路徑情況,再以通道匹配濾波器對訊號做最佳合成。所提出之新型互補碼解調變電路架構,以synopsys之design analysis最佳化與快速華許方塊解調變電路架構做比較,在運作時間延遲不變下,硬體要求為0.53倍,成功改善硬體要求。
In recent years, the way of the data transmission has been upgraded to the wireless communication with technology progress. Many wireless communication systems have been proposed, as the Wireless LAN IEEE 802.11.The data rates of the IEEE 802.11 were 1Mbps and 2Mbps in first, since the data transmission of the Wireless communication is the multimedia transmission now, so the data rates about 1Mbps and 2Mbps are not enough. A new communication system about the IEEE 802.11b was proposed, the data rates of the IEEE 802.11b were 5.5Mbps and 11Mbps. Since the data rate of the IEEE 802.11b was improved, the effect of the channel as noise, interference and mutipath will be obvious. The signal will be indistinct, and the SNR will be reduced.
The study of this thesis is to analyse and simulate the design of receiver baseband circuits of the wireless LAN IEEE 802.11b as Timing Recovery circuit, Rake circuit and a new CCK Demodulator circuit by Verilog and Matlab. Timing Recovery circuit is import for the running of the receiver circuit correctly, and provides the clock of other circuit by the recovery form the perfect correlation of Barker Code. Rake circuit is constructed from the Channel Estimator and the Channel Matched Filter. To base on the detected station of the channel by the Channel Estimator, the signal was composed perfectly by the Channel Matched Filter. A new structure of CCK Demodulator was proposed. It was the better in hardwave implementation than the Fast Walsh Block structure. By the simulator of the optimization of the design analysis in Synopsys, the request for hard implementation of the new structure of CCK Demodulator was 0.53 times of the request of the Fast Walsh Block structure, and their time Delay were approximate.
目錄
中文摘要……………………………………………………….……...i
英文摘要………………………………………………………..……..iii
誌謝………………………………………………………………..…..v
目錄………………………………………………………………..…..vi
圖目錄……………………………………………………….…..…….ix
表目錄……………………………………………………….………..xii
第一章 緒論 1
1.1 無線區域網路之簡介 1
1.2 通道簡介[1] 3
1.3 研究重點與章節 5
第二章 無線區域網路基頻架構 6
2.1 系統簡介 6
2.2 傳送端封包格式 6
2.3 調變技術 8
2.4 發射端基頻架構 12
2.5 接收端基頻架構 14
第三章 時序回復與訊號同步 17
3.1 訊號同步簡介 17
3.2 同步訊號產生時之相關電路 17
3.3 Barker Code解調變器 20
3.4 時序控制器 22
第四章 RAKE 26
4.1 通道特性 27
4.2 通道模型 27
4.3 IEEE 802.11之通道模型 28
4.4 RAKE原理 30
4.5 多路徑偵測 32
4.6 RAKE架構 35
4.7 RAKE設計評估 37
第五章 互補碼解調變之新架構 41
5.1 互補碼簡介 41
5.2 互補碼調變 43
5.3 互補碼解調變 45
5.4 快速華許解調變架構 47
5.5 新型解調變架構 55
5.6 硬體分析 62
第六章 模擬結果 66
6.1 時序回復 66
6.2 RAKE 70
6.3 新型互補碼解調變 71
6.4 硬體面積模擬結果 73
第七章 結論 74
7.1 回顧 74
7.2 未來研究方向 75
參考文獻 76
參考文獻
[1] Yi-Ling Chao, “Design Consideration of Channel Characteristics and RAKE Receiver on High Speed Wireless LAN”, CCL Technical Journal, 5. 5. 1999.
[2] IEEE Std. 802.11, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications ”, November 1997.
[3] Richard, van Nee, “OFDM Codes for Peak-to-Average Power Reduction and Error Correction”, IEEE Global Telecommunications Conference, November 18-22, 1996, pp. 740-744.
[4] Jen-Shi Wu, Ming-Luen Liou, His-Pin Ma, and Tzi-Dar Chiueh, “A 2.6V, 44MHz All Digital QPSK Direct Sequence Spread Spread Transceiver IC”, IEEE Journal of Solid State Circuits, vol. 32, no. 10, pp. 1499-1510, October 1997.
[5] Sheng-Zong Wu, “Baseband DSSS QPSK Transceiver for Wireless LAN”, Master thesis, Dept. of Electrical Engineering, National Taiwan University, June 1997.
[6] Richard van Nee, “Delay Spread Requirements for Wireless Networks in the 2.4GHz and 5 GHz Bands”, IEEE P802.11-97/125.
[7] Naftali Chayat, “Tentative Criteria for Comparison of Modulation Methods”, IEEE P802.11-97/96.
[8] Shu-Mei Li, “Design and Implementation of CCK8 Modulation Baseband Processor for High Speed Wireless LAN”, Master thesis, Dept. of Electrical Engineering, National Taiwan University, June 2000.
[9] Golay, M.J.E., “Static Multislit Spectrometry and it’s Application to the Panoramic Display of Infrared Spectra”, J. Opt. Soc. Am, Vol. 41, No. 7, pp. 468-472; July 1951.
[10] Carl Andren and Mark Webster, “CCK Modulation Delivers 11Mbps for High Rate IEEE 802.11 Extension”, Wireless Symposium/Portable by Design Conference, Spring 1999.
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top