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研究生:王維倫
研究生(外文):Wei-Lun Wang
論文名稱:嵌入式記憶體測試與內建式自我測試系統之設計與實現
論文名稱(外文):On the Design and Implementation of Embedded Memory Testing and Built-In Self-Test Schemes
指導教授:李昆忠李昆忠引用關係王駿發
指導教授(外文):Kuen-Jong LeeJhing-Fa Wang
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:90
語文別:英文
中文關鍵詞:系統單晶片
外文關鍵詞:system-on-a-chip
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  • 被引用被引用:0
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  • 收藏至我的研究室書目清單書目收藏:1
在本論文中,我們主要在於研究系統單晶片(system-on-a-chip)之嵌入式記憶體及邏輯核心電路可測試性技術及自我測試架構之電路設計。
由於行進式測試演算法(march testing algorithm)是以循序方式進行對各個記憶體元件(memory cell)進行測試,因此行進式測試演算法廣泛應用於系統單晶片之嵌入式記憶體及獨立型記憶體的測試。當行進式測試演算法是用來測試資料匯流排為位元組的記憶體(word-oriented memory)時必須用到背景資料(data background)以對記憶體的資料匯流排進行測試,在本論文中我們首先將兩個常用不同形式的背景資料進行分析並設計一個電路架構藉著簡單控制信號來產生背景資料以降低硬體成本。緊接著我們提出一個有效方法以整合四十個行進式測試演算法並且設計於單一電路架構中,並可用於測試各種不同資料匯流排寬度的記憶體,如此將具有低成本及易於操作使用等優點。每一個行進式記憶體測試演算法是由一群上下位址順序信號、讀寫控制信號、讀寫資料、以及讀寫作用長度等作為控制信號來對記憶體進行測試,這些控制信號將儲存在電路中以便即時對記憶體進行測試,我們在論文中也提出一個化簡方法以減少控制信號的儲存量。配合行進式測試演算法的特性,此一電路架構的核心部分我們是採用一對可程式化的循環式位移暫存器(programmable cyclic shift register)如此可以週而復始地產生各種行進式測試演算法的讀寫信號及資料。我們所提出的記憶體測試向量產生器不僅可以適用於四十個行進式測試演算法亦可適用於其他或是未來正在發展中的行進式測試演算法。
其次在嵌入式邏輯核心電路可測性設計方面,由於線性回授位移暫存器(linear feedback shift register)廣泛地應用於測試向量產生器及測試響應壓縮電路,為解決線性回授位移暫存器的初值(initial value)設定及終值(final value)觀察等問題,我們提出一個混合型回授位移暫存器(mixed-type feedback shift register)的架構。混合型回授位移暫存器架構與線性回授位移暫存器的架構非常類似,其主要差別在於混合型回授位移暫存器內部兩個相鄰的D型正反器(D flip-flop)的輸出端可以為正相輸出(true output)或者是反相輸出(complementary output)而傳統的線性回授位移暫存器僅使用正相輸出,如此混合型回授位移暫存器具有較大的彈性不僅可以產生與線性回授位移暫存器相同的測試向量而且可以設定使用者所期望的初值。混合型回授位移暫存器不僅可以適用於測試向量產生器亦可用於測試響應壓縮電路之設計,並且具有初值及終值隨選(seed-and-signature-on-demand)的功能,可以讓使用者依據需求設定初值及終值來進行測試工作以減輕測試工程師的負擔。
為減少數位電路的測試成本,在掃描型植入式自我測試的環境中, 線性回授位移暫存器可以用來產生虛擬隨機測試向量(pseudorandom test vector)及特定測試向量(deterministic test vector)。然而就跟其他掃描型架構一樣,線性回授位移暫存器所產生的測試向量需要很長的時間方能放入掃描鏈。在本論文中我們推導出掃描鏈的位元值與線性回授位移暫存器的狀態關係並且證明了由線性回授位移暫存器所產生的輸出值可以藉著其內部狀態的線性函數(linear function)提早產生並放入掃描鏈。基於此,我們證明了任何一個掃描鏈均可被分割成若干個次掃描鏈(sub-chain)並且可以同時輸入由相同的線性回授位移暫存器依據線性函數所產生的序列,如此可以減少測試時間進而節省測試能量。
In this dissertation, we present several built-in self-test (BIST) schemes for testing the embedded memory and logic cores in the system-on-a-chip (SOC) designs.
Due to the memory cells can be tested in a regular address order, the march algorithms are popular to test the embedded memory cores of the SOC and stand-alone memories. For testing the word-oriented memories, two kinds of data backgrounds are coupled with specific march algorithms, respectively, to raise fault coverage. To achieve satisfied high fault coverage, these data backgrounds with march algorithms are used in different testing phases. To reduce the hardware cost of the data background generator, we firstly analyze the properties of two frequently used data backgrounds and find these data backgrounds can be integrated into a single circuitry. Then we propose an effective approach to integrate 40 existing march algorithms into an embedded low hardware overhead test pattern generator to test the various kinds of word-oriented memory cores. Each march algorithm is characterized by several sets of up/down address orders, read/write signals, read/write data, and lengths of read/write operations. These characteristics are stored on chip so that any desired march algorithm can be generated with very little external control. An efficient procedure to reduce the memory storage for these characteristics is presented. We use only two programmable cyclic shift registers to generate the various read/write signals and data required by all algorithms. Therefore the proposed pattern generator is capable of executing any march algorithm with small area overhead.
A mixed-type feedback shift register (MFSR) is similar to a linear feedback shift register (LFSR) except that the connection between two consecutive flip-flops may be through the Q or output, and an extra inverter may exist at the input to the first flip-flop of the register. In this dissertation we exploit the properties of MFSRs and show that by using an MFSR based pseudorandom pattern generator (PRPG) or multiple-input signature analyzer (MISA), several good BIST features can be obtained, for example the seed (seed and signature) controllability of the MFSR based PRPG (MISA) is higher than the LFSR based PRPG (MISA), thus relieving the burden of test engineers.
To obtain satisfactory fault coverage for testing a logic circuit, LFSRs have been used to generate not only the pseudorandom, but also the deterministic patterns in the scan-based BIST environment. However, like other scan-based methods, the LFSR based pattern generation schemes take a long test application time to feed deterministic patterns from the LFSR into a scan chain. In this dissertation we derive a general relationship between the bits in the scan chain and the states of the LFSR and show that any bit to be generated by an LFSR in any future clock cycle can be pre-generated by a linear function of the current LFSR state. With this relationship, we can divide a scan chain into multiple sub-chains and use one LFSR-based multiple sequence generator to simultaneously generate all the subsequences required by the sub-chains, hence can greatly reduce the test application time for deterministic patterns. Moreover, due to the scan time reduction, test energy wasted during the scan operation can also be significantly reduced.
Chapter 1Introduction 1
1.1 Memory BIST Schemes 2
1.2 Logic BIST Schemes 3
1.3 Organization of the Dissertation 6
Chapter 2Data Backgrounds for Word-Oriented Memory Testing 7
2.1 Introduction 7
2.2Notations of March Algorithms 9
2.3Analyzing and Building DB1 and DB2 10
2.4Concluding Remarks 17
Chapter 3Data Backgrounds for Word-Oriented Memory Testing 18
3.1 Introduction 18
3.2Review of March Algorithms 20
3.3Reduction of Read/Write Operations 21
3.4 Architecture of The Proposed Test Pattern Generator 24
3.5 The Working Procedure of the Proposed TPG 29
3.6 Simulation Results 31
3.7 Concluding Remarks 33
Chapter 4The Mixed-Type Feedback Shift Registers 35
4.1 Introduction 35
4.2 Linear Feedback Shift Registers 38
4.3Mixed-Type Feedback Shift Registers 39
4.4 MFSR Based Pseudorandom Pattern Generators 42
4.5 Multiple Input Signature Analyzers (MISAs) 50
4.5.1 LFSR Based MISAs 50
4.5.2 MFSR Based MISAs 51
4.5.3 Consideration on the Dummy Pattern 57
4.6 Concluding Remarks 57
Chapter 5Accelerated Deterministic Test Pattern Generator for Scan-Based BIST 59
5.1 Introduction 59
5.2 Basic Idea of the Proposed Test Pattern Generators 61
5.3 Accelerated Test Pattern Generators 65
5.4 Experimental Results 71
5.5 Reduction in Test Power 77
5.6 Concluding Remarks 78
Chapter 6Conclusions 80
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