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研究生:黃宗柱
研究生(外文):Tsung-Chu Huang
論文名稱:CMOS邏輯電路之低功率測試
論文名稱(外文):Low Power Testing for CMOS Logic Testing
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:118
中文關鍵詞:低功率測試超大型積體電路測試易測試性設計功率消耗掃描式電路內建自我測試系統單晶片測試測試功率
外文關鍵詞:Low power testVLSI testDesign for TestabilityPower dissipationScan based circuitsBuilt-In Self-TestSOC testTest power
相關次數:
  • 被引用被引用:1
  • 點閱點閱:1156
  • 評分評分:
  • 下載下載:244
  • 收藏至我的研究室書目清單書目收藏:2
在系統單晶片(SOC)的時代,電晶體密度的提高與操作速度的增加使得功率消耗成為測試時一項關鍵性的問題。本論文主要針對此一問題,提出四項技術以減少CMOS邏輯電路在測試時的功率消耗。茲摘要此四項技術如下:
首先,我們提出輸入端控制技術(Input control technique),此技術採用一個類似D演算法的方法來產生一個控制向量,在掃描電路時輸入在主輸入端,以便儘量阻斷掃描時的跳動,降低組合邏輯電路的平均功率消耗。此技術可以與既有之向量排序法與栓鎖排序法並用。實驗結果顯示,既有之向量與栓鎖排序法可以減少22.37%的功率消耗;當在栓鎖與向量排序法之後採用輸入端控制技術時,將可降低34.23%的平均功率。
其次,在降低多鏈掃描電路的尖峰功率方面,我們提出一項錯開掃描技術(Interleaving scan technique)。此技術主要藉由在各掃描鏈間加入一或兩個D型正反器作為延遲緩衝器以錯開各掃描鏈之尖峰功率發生的時間,使整體尖峰功率得以有效降低。由實驗得知,當掃描元件的資料輸出會受到掃描輸出影響時,最高可降低51%的尖峰功率;當掃描元件的資料輸出不會受到掃描輸出影響時,最高可降低76%的尖峰功率。
第三種技術提出一種符記掃描架構(Token scan architecture),此架構結合多相時序、符記環及時脈閘控等三項技術,以降低資料跳動、減輕繞線及相間時差(Skew) 的問題、並消除廣播型態之功率消耗。由實驗得知,當掃描鏈很長時,平均功率將可降低超過95%。
另外,我們也對內建自我測試提出一種低功率消耗的多相混成線性回授移位暫存器(Multiphase hybrid LFSR)。由於前人之多相線性回授移位暫存器需要比較複雜的多相時脈產生器及控制邏輯電路與傳輸閘式的多工器,使得功率降低率有限。我們設計了一個由栓鎖式強生計數器所實現之多相時脈產生器,並使用靜態邏輯閘所組合之解多工器,提出一個單相與多相混成之線性回授移位暫存器。由評估分析中得知,當正反器個數大於27時,我們的架構比前人的方法降低40%的功率消耗;若是與傳統單相之設計比較,將可降低70%的功率消耗。
整體而言,輸入端控制技術主要目的在降低測試時的平均功率消耗;相對的,錯開掃描技術可以有效降低尖峰功率;符記掃描架構與多相混成線性回授移位暫存器則可以有效降低平均功率而其尖峰功率降低率也很可觀。最後我們將此四種技術的功率降低率與其應用性列表討論,並經由這些分析提出未來改進與研究的方向。

The increasing transistor density and operating speed in the system-on-a-chip (SOC) era make the power dissipation during test a critical issue. This dissertation proposes four techniques to reduce the power dissipation in test application time for CMOS logic circuits.
First, we propose an input control technique that employs a D-algorithm-like approach to generate a control pattern which, when applied at the primary inputs during scan operations, can minimize the switching activity of full-scan circuits. This technique can be utilized together with the existing vector ordering or latch ordering techniques. Experimental results show while the vector ordering and the latch ordering techniques can achieve 22.37% of average power reduction, 34.23% average improvement can be achieved if the input control technique is employed after the latch ordering and vector ordering techniques.
Second, an interleaving technique is proposed to reduce the peak power of multiple scan chain based circuits during testing. A test architecture is presented which can significantly reduce the peak power by adding delay buffers among the scan chains. This method can be efficiently integrated with a recently proposed broadcast multiple scan architecture due to the sharing of scan patterns. The effects of the interleaving scan technique applied to the conventional multiple scan and the broadcast multiple scan with 10 scan chains are investigated. Up to 51\% peak power reduction can be achieved when the data output of a scan cell is affected by the scan path during scan. When the data output is disabled during scan, up to 76% of peak-power reduction is observed.
Third, a novel token scan architecture is developed which employs the concepts of multiphase clocking, token ring and clockgating to minimize the data transitions, to alleviate the routing and skew problems, and to eliminate the broadcasting dissipation on the clock tree and scan-in data tree during scan operations. This token scan architecture can efficiently reduce the data transitions in the scan circuits as well as the switching activity in both the clock and the scan-in data trees. From experiments, more than 95% of power reduction can be achieved for most circuits with long scan chains.
Fourth, we observe that previously multiphase LFSR schemes have been proposed to reduce the data transitions during test and signal process. However, due to the more complex clock generator, the broadcasting input and the multiplexing output, the power reduction is actually much limited. We propose a new LFSR architecture to improve the power reduction via developing a novel low-power and cost-effective Johnson counter for the multiphase clock generator and employing static logic gates to implement the output multiplexer. To reduce the stages of the multiphase clock generator and the area of the multiplexer, a hybrid LFSR design combining both single and multiple phase clocks is developed. From our evaluation, our architecture has 40\% more power reduction than the previous $n$-phase LFSR architecture when $n$ is greater than 27 and up to 70% power reduction compared to a conventional LFSR.
In summary, the input control technique is mainly for reducing the average power dissipation while the interleaving technique is for the peak power. Both the token scan architecture and the hybrid LFSR scheme can reduce average power as well as peak power. To conclude this dissertation, we tabulate the reduction efficiency of our techniques and analyze their applicability and suitability. Based on the analysis, some future work is suggested.

1 Introduction
1.1 Overviews of the Proposed Techniques
1.2 Organization of the Dissertation
2 Previous Work
2.1 BIST Scheduling Approaches
2.2 Approaches Characterized by Test Generation
2.2.1 Pre-ATPG Approach
2.2.2 In-ATPG Approach
2.2.3 Post-ATPG Approach
2.3 Vector Inhibiting or Transition Masking
2.3.1 Vector Inhibiting Technique
2.3.2 Input Control or Freezing
2.3.3 Data Output Disabled Scan Cells
2.4 Partitioning or Splitting Strategies
2.4.1 Circuit Partitioning
2.4.2 Register or Chain Splitting
2.5 Partial Scan Insertion or Selection Strategies
2.6 Integration of Low Power Testing Approaches
2.7 Summary
3 Models and Definitions
3.1 Power Dissipation Model
3.2 Full Scan Model
4 Input Control Technique
4.1 Preliminaries
4.2 Input Control Technique
4.2.1 C-Algorithm
4.2.2 Evaluation of the C-algorithm and a Control Strategy
4.3 Experimental Results
4.4 Summary
5 Interleaving Scan Technique
5.1 Basic Concept
5.2 Designs for the Interleaving Scan
5.2.1 Conventional Multiple Scan Structures
5.2.2 Broadcast Multi-scan Circuits
5.3 Experimental Results
5.4 Summary
6 Token Scan Architecture
6.1 Preliminary Notations
6.2 Token Scan Architecture
6.2.1 Token Scan Cell Design
6.2.2 Token Gating Cell Design
6.2.3 An Example
6.3 Experimental Results
6.4 Summary
7 Multiphase Linear Feedback Shift Registers
7.1 A Low-Power Multiphase LFSR
7.1.1 A Low-Power Cost-Effective Multiphase Generator
7.1.2 Low-Power Multiplexers
7.2 A Hybrid LFSR Design
7.3 Evaluation
7.4 Summary
8 Conclusions and Future Work
8.1 Comparison of Proposed Techniques
8.2 Conclusions and Future Work

L. Whetsel. Addressable Test Ports - an Approach to Testing Embedded Cores. Proc. International Test Conference, pages 1055-1064, 1999.
A. P. Chandrakasan, S. Sheng, and R. W. Brodersen. Low-Power CMOS Digital Design. IEEE Jounal of Solid-State Circuits, 27(4):473-484, Apr. 1992.
C.-W. Wu. On Energy Efficiency of VLSI Testing. Proc. Asian Test Symposium, pages 132-137, 1997.
M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital System Testing and Testable Design. Computer Science Press, 1990.
Y. Zorian. A Distributed BIST Control Scheme for Complex VLSI Devices. Proc. VLSI Test Symposium, pages 4-9, 1993.
J. Hirase and M. Hamada. The Effect of Fault Detection by IDDQ Measurement for CMOS VLSIs. Proc. Asian Test Symposium, pages 144-149, 1994.
R. R. Fritzemeier, J. M. Soden, and R. K. Treece. Increased CMOS IC Stuck-at Fault Coverage with Reduced IDDQ Sets. Proc. International Test Conference, pages 427-434, 1990.
S. Gerstendorfer and H.-J. Wunderlich. Minimized Power Consumption for Scan-based BIST. Proc. International Test Conference, pages 77-84, 1999.
P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. Proc. Asian Test Symposium, pages 89-94, 1999.
P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. A Test Vector Inhibiting Technique for Low Energy BIST Design. Proc. VLSI Test Symposium, pages 407-412, 1999.
N. Nicolici and B. M. Al-Hashimi. Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. Proc. European Design and Test Conference, pages 715-722, 2000.
P. Girard. Low Power Testing of VLSI Circuits: Problems and Solutions. IEEE International Symposium on Quality Electronic Design, pages 173-179, 2000.
S. Chakravarty and V. P. Dabholkar. Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Application. Proc. Asian Test Symposium, pages 324-329, 1994.
X. Zhang and K. Roy. Peak Power Reduction in Low Power BIST. IEEE 1st International Symposium on Quality Electronic Design, pages 425-432, 2000.
A. Macii, E. Macii, and M. Poncino. Reducing Peak Power Consumption of Combinational Test Sets. 32nd Asilomar Conference on Signals, Systems and Computers, pages 1042-1046, 1998.
A. Macii and E. Macii. Peak Power Constrained Test Sets: Generation Heuristics and Experiments. Sixth IEEE International Conference on Electronics, Circuits and Systems, pages 925-928, 1999.
F. Corno, M. Rebaudengo, M. Sonza Reorda, and M. Violante. Transformation-based Peak Power Reduction for Test Sequences. IEEE Alessandro Volta Memorial Workshop on Low-power Design, pages 78-83, 1999.
S. Wang and S. K. Gupta. LT-RTPG: A New Test-Per-Scan BIST TPG for Low Heat Dissipation. Proc. International Test Conference, pages 85-94, 1999.
M. S. Hsiao. Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits. Proc. European Design and Test Conference, pages 175-179, 1999.
X. Zhang and K. Roy. Design and Synthesis of Low Power Weighted Random Pattern Generation Considering Peak Power Reduction. International Symposium on Defect and Fault Tolerance in VLSI Systems, pages 148-156, 1999.
T.-C. Huang and K.-J. Lee. Test Power Reduction During Scan Operation Via Input Control. The 10th VLSI Design/CAD Symposium, pages 107-110, Aug. 1999.
T.-C. Huang and K.-J. Lee. An Input Control Technique for Power Reduction in Scan Circuits During Test Application. The Eighth Asian Test Symposium, pages 315-320, Nov. 1999.
T.-C. Huang and K.-J. Lee. Reduction of Power Consumption in Scan-based Circuits during Test Application by an Input Control Technique. IEEE Trans. on Computer-Aided Design of Circuits and Systems, 20(7):911-917, July 2001.
T.-C. Huang and K.-J. Lee. Interleaving Multiple Scan Technique to Reduce Peak-Power. The 11th VLSI Design/CAD Symposium, pages 385-388, Aug. 2000.
K.-J. Lee, T.-C. Huang, and J.-J. Chen. Peak-Power Reduction for Multiple-Scan Circuits during Test Application. Proc. Asian Test Symposium, pages 453-458, Dec. 2000.
T.-C. Huang and K.-J. Lee. An Interleaving Technique for Reducing Peak Power in Multiple-Chain Scan Circuits during Test Application. To be published in Journal of Electronic Testing - Theory and Applications, May 2001.
T.-C. Huang and K.-J. Lee. Token Scan Cell for Low Power Testing. IEE Electronics Letters, 31(17):678-679, May 2001.
T.-C. Huang and K.-J. Lee. A Token Structure for Low Power Scan Design. The 12th VLSI Design/CAD Symposium, pages A3-1, Aug. 2001.
T.-C. Huang and K.-J. Lee. A Token Scan Architecture for Low Power Testing. Proc. International Test Conference, pages 660-669, Oct. 2001.
M. Lowy and K. Anne. A High Speed, Low Power Spread Spectrum Code Generator. Proc. 37th Midwest Symposium on Circuits and Systems, volume 1, pages 23-26, 1995.
M. Lowy. Parallel Implementation of LFSR for Low Power Applications. IEEE Trans. on Circuits and Systems, 43(6):458-466, June 1996.
T.-C. Huang and K.-J. Lee. A Hybrid LFSR Design for Low Power Applications. To be published in Journal of the Chinese Institute of Electrical Engineering, Nov. 2001.
T.-C. Huang and K.-J. Lee. A Low-Power LFSR Architecture. Proc. Asian Test Symposium, Nov. 2001.
W.-L. Wang and K.-J. Lee. Acclerated Test Pattern Generators for Mixed-Mode Environments. Proc. Asian Test Symposium, pages 368-373, 2000.
H.-C. Tsai, S. Bhawmik, and K.-T. Cheng. An Almost Full-Scan BIST Solution - Higher Fault Coverage and Shorter Test Application Time. Proc. International Test Conference, pages 1065-1073, 1998.
R. M. Chou, K. K. Saluja, and V. D. Agrawal. Power Constraint Scheduling of Tests. Proc. Conference on VLSI Design, pages 271-274, 1994.
R. M. Chou, K. K. Saluja, and V. D. Agrawal. Scheduling Tests for VLSI Systems Under Power Constraints. IEEE Trans. on VLSI Systems, 5(2):175-185, June 1997.
G. L. Craig, C. R. Kime, and K. K. Saluja. Test Scheduling and Control for VLSI Built-In Self-Test. IEEE Trans. on Computers, 37(9):1099-1109, Sep. 1988.
T. C. Wilson, A. Basu, D. K. Banerji, and J. C. Majithia. Test Plan Generation and Concurrent Scheduling of Tests in the Presence of Conflicts. IEEE Symposium on VLSI, pages 243-248, 1991.
A. P. Strole and H.-J. Wunderlich. Signature Analysis and Test Scheduling for Self-Testable Circuits. Fault Tolerant Computing Symp., pages 96-103, 1991.
C.-I. H. Chen and J. T. Yuen. Concurrent Test Scheduling in Built-In Self-Test Environment. International Conference on Computer Design, pages 256-259, 1992.
J. Y. Sayah and C. R. Kime. Test Scheduling in High Performance VLSI System Implementation. IEEE Trans. on Computers, 41(1):52-67, Jan. 1992.
I. G. Harris and A. Orailoglu. Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST. Proc. European Design and Test Conference, pages 113-123, 1194.
D. Xiang. Test Scheduling using Test Subsession Partitioning. Proc. Asian Test Symposium, pages 63-68, 1994.
Y. Huang, W.-T. Cheng, C.-C. Tsai, and N. Mukherjee. Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SOC Design. Proc. Asian Test Symposium, pages 265-270, 2001.
K. Chakrabarty. Test Scheduling for Core-based Systems using Mixed-Integer Linear Programming. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19(10):1163-1174, Oct. 2000.
V. Muresan, Xiaojun Wang, V. Muresan, and M. Vladutiu. A Comparison of Classical scheduling Approaches in Power-Constrained block-test scheduling. Proc. International Test Conference, pages 882-891, 2000.
V. Iyengar and K. Chakrabarty. Precedence-Based, Preemptive and Power-Constrained Test Scheduling for System-on-a-Chip. Proc. VLSI Test Symposium, pages 368-374, 2001.
P. M. Rosinger, B. M. Al-Hashimi, and N. Nicolici. Power Constrained Test Scheduling using Power Profile Manipulation. Proc. European Design and Test Conference, pages 251-254, 2001.
K.-J. Lee, J.-J. Chen, and C.-H. Huang. Broadcasting Test Patterns to Multiple Circuits. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 18(12):1793-1802, Dec. 1999.
K.-J. Lee, J.-J. Chen, and T.-C. Huang. Test Power Reduction for Scan-Based Design. The 12th VLSI Design/CAD Symposium, pages A3-10, Aug. 2001.
S. Wang and S. K. Gupta. ATPG for Heat Dissipation Minimization During Test Application. Proc. International Test Conference, pages 250-258, 1994.
S. Wang and S. K. Gupta. ATPG for Heat Dissipation Minimization during Scan Testing. Design Automation Conference, pages 614-619, 1997.
F. Corno, P. Prinetto, M. Rebaudengo, and M. Sonza Reorda. A Test Pattern Generation Methodology for Low Power Consumption. Proc. VLSI Test Symposium, pages 453-457, 1998.
S.-A. Hwang and C.-W. Wu. Low-Power Testing for C-testable Iterative Logic Arrays. Proc. Symposium on VLSI, pages 355-358, 1998.
V. Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy. Techniques for Minimizing Power Dissipation in Scan and Combinational Circuits During Test Application. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 17(12):1325-1333, Dec. 1998.
P. Girard, C. Landrault, S. Pravossoudovitch, and D. Severac. Reduction of Power Consumption during Test Application by Test Vector Ordering. Electronics Letters, 33(21):1752-1754, Oct. 1997.
P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. A Test Vector Ordering Technique for Switching Activity Reduction during Test Operation. The Ninth Great Lakes Symposium on VLSI, pages 24-27, 1999.
H. Cheung and S. K. Gupta. A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation. Proc. International Test Conference, pages 386-395, 1996.
K.-J. Lee, J.-J. Tang, and T.-C. Huang. BIFEST: A Built-in Intermediate Fault Effect Sensing and Test Generation System for CMOS Bridging Faults. ACM Trans. on Design Automation and Electronic System, 4(2):194-218, Apr. 1999.
N. Nicolici, B. M. Al-Hashimi, and A. C. Williams. Minimisation of Power Dissipation during Test Applicaiton in Full Sequential Circuits using Primary Input Freezing. IEE Proc. on Computer and Digital Techniques, 147(5):313-322, Sep. 2000.
A. Hertwig and H.-J. Wunderlich. Low Power Serial Built-In Self-Test. IEEE European Test Workshop, pages 49-53, 1998.
L. Jin. Low Power Scan Test Cell and method for Making the Same. US Patent. 6,114,892, 2000.
M. A. Breuer, M. Sarrafzadeh, and F. Somenzi. Fundamental CAD Algorithms. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 19(12):1449-1475, Dec. 2000.
P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. Low Power BIST Design by Hypergraph Partitioning: Methodology and Architectures. Proc. International Test Conference, pages 652-661, 2000.
S. Wang and S. K. Gupta. DS-LFSR: A New BIST TPG for Low Heat Dissipation. Proc. International Test Conference, pages 848-857, 1997.
L. Whetsel. Adapting Scan Architectures for Low Power Operation. Proc. International Test Conference, pages 863-872, 2000.
L. Xu, Y. Sun, and H. Chen. Low-Power Technique of Scan-Based Design for Test. Electronics Letters, 36(23):1920-1921, Nov. 2000.
L. Xu, Y. Sun, and H. Chen. Scan Array Solution for Testing Power and Testing Time. Proc. International Test Conference, pages 652-659, 2001.
J. Saxena, K. M. Butler, and L. Whetsel. An Analysis of Power Reduction Techniques in Scan Testing. Proc. International Test Conference, pages 670-677, 2001.
P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. J. Wunderlich. A modified Clock Scheme for a Low Power BIST Test Pattern Generator. VLSI Test Symposium, pages 306-311, 2001.
Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch. A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. Proc. Asian Test Symposium, pages 253-258, Nov. 2001.
S. Barbagallo, M. Lobetti Bodoni, D. Medina, F. Corno, P. Prinetto, and M. Sonza Reorda. Scan Insertion Criteria for Low Design Impact. Proc. VLSI Test Symposium, pages 26-31, 1996.
J.-Y. Jou and M.-C. Nien. Power Driven Partial Scan. IEEE International Conference on Computer Design, pages 642-647, 1997.
J.-Y. Jou and M.-C. Nien. Power-Oriented Partial-Scan Design Approach . IEE Proc. on Computer and Digital Techniques, 145(4):229-235, Aug. 1998.
N. Nicolici and B. M. Al-Hashimi. Minimising Power Dissipation in Partial Scan Sequential Circuits. IEE Proc. on Computer and Digital Techniques, 148(4-5):163-166, July-Sep. 2001.
E. Larsson and Z. Peng. Test Scheduling and Scan-Chain Division under Power Constraint. Proc. Asian Test Symposium, pages 259-264, Nov. 2001.
J. Aerts and E. J. Marinissen. Scan Chain Design for Test Time Reduction in Core-Based ICs. Proc. International Test Conference, pages 448-457, 1998.
N. Nicolici and B. M. Al-Hashimi. Power Conscious Test Synthesis and Scheduling for BIST RTL Data Paths. Proc. International Test Conference, pages 662-671, 2000.
S.-C. Chang, K.-J. Lee, Z.-Z. Wu, and W.-B. Jone. Reducing Test Application Time by Scan Flip-Flops Sharing. IEE Proc. on Computer and Digital Techniques, 147(1):42-48, Jan. 2000.
N. Nicolici and B. M. Al-Hashimi. Tackling Test Tradeoffs for BIST RTL Datapaths: BIST Area Overhead, Test Application Time and Power Dissipation. Proc. International Test Conference, pages 73-82, 2001.
N. Weste and K. Eshraghian. Principles of CMOS VLSI Design. Addison-Wesley, Mass., 1993.
M. Pedram. Power minimization in IC Design: Principles and Applications. ACM Trans. Design Automation Electronic System, 1(1):3-56, Jan. 1996.
Q. Wang and S. Vrudhula. A New Short Circuit Power Model for Complex CMOS Gates. International Symposium on Low Power Design, pages 98-106, 1999.
F. N. Najm. Transition Desity: A New Measure of Activity in Digital Circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 12(2):310-323, Feb. 1993.
F. N. Najm. A Survey of Power Estimation Techniques in VLSI Circuits. IEEE Trans. on VLSI Systems, 2:446-455, Dec. 1994.
D. Brand and C. Visweswariah. Inaccuracies in Power Estimation During Logic Synthesis. IEEE International Conference on CAD, pages 6C-1, 1996.
K. I. Diamantaras and N. K. Jha. A New Transition Count Method for Testing of Logic Circuits. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, 10(3):407-410, Mar. 1991.
F. N. Najm. Transition Density, A Stochastic Measure of Activity in Digital Circuits. Design Automation Conference, pages 644-649, 1991.
K. Roy and S. Prasad. Circuit Activity Based Logic Synthesis for Low Power Reliable Operations. IEEE Trans. VLSI Systems, 1(4):503-513, Dec. 1993.
K.-J. Lee, M.-H. Lu, and J.-F. Wang. A Systematic Method to Classify Scan Cells. Proc. Asian Test Symposium, pages 219-224, 1993.
E. B. Eichelberger and T. W. Williams. A Logic Design Structure for LSI Testing. Proc. Design Automation Conf., pages 462-468, 1977.
C. T. Glover and M. R. Mercer. A Method of Delay Fault Test Generation. Proc. Design Automation Conf., pages 83-90, 1988.
E. L. Lawler, J. K. Lenstra, A. H. G. Rinnoy Kan, and D. B. Shmoys. The Traveling Salesman Problem. John Wiley and Sons, 1985.
R. Sedgewick. Algorithms. Addison-Wesley, 1983.
G. De Micheli. Synthesis and Optimization of Digital Circuits. McGraw-Hill, N.Y., 1994.
Avanti Co. Meta-Model of 0.35um 1P4M Standard Cell Library. Ver.3.41, U.S., 1998.
N. Sedgewick. Algorithms for VLSI Physical Design Automation. Kluwer, Boston, 1993.
M. R. Garey and D. S. Johnson. Computers and Intractability - A Guide to the Theory of NP-Completeness. Freeman, N.Y., 1979.
J. A. Waicukauski, E. B. Eichelberger, D. O. Forlenza, E. Lindbloom, and T. McCarthy. Fault Simulation for Structured VLSI. VLSI System Design, pages 20-32, 1985.
D. Harris. Skew-Tolerant Circuit Design. Academic Press, San Diego, 2001.
A. Attarha and M. Nourani. Testing Interconnects for Noise and Skew in Gigahertz SoCs. Proc. International Test Conference, pages 305-314, 2001.
D. Liu and C. Svensson. Power Consumption Estimation in CMOS VLSI Circuits. IEEE J. Solid-State Circuits, 29:663-670, June 1993.
S. Pullela, N. Menezes, and L. T. Pillage. Low Power IC Clock Tree Design. IEEE Custom IC Conf., pages 263-266, 1995.
Q. Wu, M. Pedram, and X. Wu. Clock-Gating and its Application to Low Power Design of Sequential Circuits. IEEE Custom IC Conf., pages 479-482, 1997.
G. E. Tellez, A. Farrahi, and M. Sarrafzadeh. Activity-Driven Clock Design for Low-Power Circuits. International Conference on CAD, pages 62-65, 1995.
A. F. Champernowne, L. B. Bushard, J. T. Rusterholz, and J. R. Schomburg. Latch-to-Latch Timing Rules. IEEE Trans. on Computers, 39(6):798-808, June 1990.
M. Lowy. A Low Power Architecture for Digital Sequence Generation. IEEE Global Telecommunications Conf., pages 636-640, 1993.
T. R. Blakeslee. Digital Design with Standard MSI and LSI, pages 115-117. Wiley-Inersci., 1975.
M. E. Hamid and C.-I H. Chen. A Note on Low-Power Linear Feedback Shift Registers. IEEE Trans. on Circuits and Systems, 45(9):1034-1037, Sep. 1998.
L.-T. Wang and E. J. McCluskey. Hybrid Designs Generating Maximum-Length Sequences. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 7(1):91-99, Jan. 1988.

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