臺灣博碩士論文加值系統

在本文中,我們提出了一種應用在砷化鎵元件上之液相化學輔助氧化法，相較於其他的氧化法，這種新穎氧化法的系統相當簡單，僅包含了溫度調節器及酸鹼值測定器，我們只要將砷化鎵晶圓放進含硝酸之成長溶液中，在低溫的環境中（從30 ℃到70 ℃），表面無特徵及均勻的氧化層就能夠可靠地成長於砷化鎵晶圓上，該氧化法除了不需要外加任何能量輔助，還擁有高成長速率成長氧化薄膜（在70 ℃下約每小時1000埃）。
藉由X光光譜分析，該氧化物的構成物質為三氧化二鎵及三氧化二砷。我們並利用金屬-氧化層-半導體結構的電流-電壓特性來探討漏電流密度及電介質強度等電特性，該氧化層之崩潰電場在順向及反向偏壓下均可大於4.5 MV/cm。
我們並且成功的應用該液相化學輔助氧化法研製出N型通道之空乏型砷化鎵金氧半場效電晶體，該砷化鎵金氧半場效電晶體之汲極電流-電壓特性具有完全夾止及飽和之特性。由於該氧化法對於砷化鎵及光阻或金屬具有良好之選擇性成長特性，我們提出了利用光阻或金屬作為遮罩之選擇性成長製程，特別是以金屬作為遮罩之選擇性成長製程，不僅可以簡化製程步驟還可以成長較穩定之氧化層並提升元件特性。目前閘極長度為1微米之砷化鎵金氧半場效電晶體具有最大轉導值90 mS/mm及最大汲極電流密度350 mA/mm，而短路電流增益截止頻率及最大震盪頻率分別為6.5 GHz及18.3 GHz。我們亦研究了該元件之高頻雜訊特性，在2.4 GHz的頻率下，該元件之本質最小雜訊指數可以小於1.6 dB。
我們亦研究了會影響砷化鎵金氧半場效電晶體直流特性及微波特性的一些效應，其中包含有元件閘極尺寸、閘極氧化層厚度及操作溫度等效應，對閘極長度為1微米之砷化鎵金氧半場效電晶體而言，將操作溫度從150 ℃降低之-50 ℃時，元件轉導值會從50 mS/mm 提升至98 mS/mm，短路電流增益截止頻率會從3.6 GHz提升至7.5 GHz，最大震盪頻率會從12 GHz提升至大於20 GHz，我們發現藉由降低閘極氧化層厚度及閘極尺寸，亦可以改善元件之直流特性及微波特性。
而隨著金氧半場效電晶體之閘極氧化層厚度持續地變薄，相對增加之閘極漏電流密度因此嚴格地限制了該元件之可靠度，因此我們探討了在不同操作溫度及不同氧化層厚度下之閘極氧化層可靠度，發現閘極漏電流密度明顯隨著降低閘極氧化層厚度及增加操作溫度而增加。而藉由上述的研究結果，我們亦建立了該氧化層在低電場下之載子傳輸模型，有助於我們了解液相化學輔助氧化法所成長氧化薄膜之載子傳輸機制。
最後，基於研究液相化學輔助氧化法及研製砷化鎵金氧半場效電晶體之成果，我們提出了一新穎的平坦化溝渠式隔離製程並應用於隔離砷化鎵金氧半場效電晶體之主動區域，該液相化學輔助氧化溝渠式隔離製程相當地簡單而且可以在低溫下進行，相較於傳統山丘式隔離製程，此溝渠式隔離製程可以獲得相當平坦之隔離區域及良好的電特性。我們並展示了利用液相化學輔助氧化法之平坦化溝渠式隔離製程及選擇性閘極氧化層成長來研製N型通道空乏型砷化鎵金氧半場效電晶體，該元件具有完全夾止及飽和的電流-電壓特性。

A new liquid phase chemical-enhanced oxidation (LPCEO) technique for gallium arsenide (GaAs) device applications has been proposed. The oxidation system is simple and low in cost which only consists of a temperature regulator and a pH meter. The GaAs wafers were only immersed in a gallium-ion-contained nitric acid solution to form the oxidized film on GaAs layer. The oxide film with good uniformity can be efficiently grown on GaAs wafer at low temperature (from 30 ℃ to 70 ℃) without any assisted energy source. A relatively high oxidation rate (∼100 nm/h) at 70 ℃ has been also achieved.
From the analysis of X-ray photoelectron spectroscopy (XPS), the oxide layers are found to be the composite of the Ga2O3 and As2O3. The electrical properties including leakage current density and dielectric strength of oxide film are both obtained from the current-voltage (I-V) characteristics of metal-oxide-semiconductor (MOS) structure. The electric breakdown field higher than 4.5 MV/cm has been obtained for both forward and reverse bias voltages.
Following the previous researches of LPCEO-oxide film, the n-channel depletion-mode GaAs MOSFET with the LPCEO technique has been successfully demonstrated. The fabricated GaAs MOSFET exhibit drain current-voltage (Ids-Vds) curves with complete pinch-off and saturation characteristics. Since the LPCEO method shows good selective oxide growth between GaAs and photoresist or metal, we propose novel selective oxidation processes by using photoresist as the mask (PR-SLPCEO) and metal as the mask (M-SLPCEO) to fabricate GaAs MOSFET. The superiority of applying M-SLPCEO process over conventional fabrication process is demonstrated for less, reliable fabrication processes and better device performance. The peak extrinsic transconductance of 90 mS/mm and maximum drain current density larger than 350 mA/mm can be achieved for 1 μ m gate-length GaAs MOSFET. The microwave characteristics of the short-circuit current gain cutoff frequency fT and the maximum oscillation frequency fmax of 6.5 GHz and 18.3 GHz can be also achieved, respectively. Experimental study of the high-frequency noise figure of the GaAs MOSFET is also investigated. The 1 μm GaAs MOSFET shows measured minimum noise figure (NFmin) of 4.7 dB and associated gain of 17.4 dB at 2.4 GHz. The use of noise de-embedding method of the device shows the NFmin of 1.6 dB at 2.4 GHz.
Furthermore, effects of device geometric size, gate oxide thickness and operating temperature on dc and microwave characteristics of the GaAs MOSFET have been discussed. For 1 μm gate length MOSFET, the transconductance was found to increase from 50 mS/mm at 150 ℃ to 98 mS/mm at -50 ℃. The fT rises from 3.6 GHz at 150 ℃ to 7.5 GHz at -50 ℃ and fmax rises from 12 GHz at 150 ℃ to larger than 20 GHz at -50 ℃. An increasing trend of dc and microwave characteristics can also be observed by reducing the gate oxide thickness and gate length.
Since the MOSFET dimensions of gate oxide thickness are continually being reduced, the increasing of gate leakage current cause serious limitations on device reliability. In order to investigate the reliability of gate oxide films under various conditions, the dependences of operating temperature and gate oxide thickness have been measured. An increase in gate leakage current density with decreasing gate oxide thickness and increasing operating temperature can be observed. According to above experimental results, we also demonstrate the transport mechanism of the LPCEO-oxide films will follow the Schottky emission and Poole-Frenkel conduction at low electrical field. The established transport model can provide useful information to realize the carrier transport mechanism of the LPCEO-oxide film.
Finally, based on the investigation of LPCEO method and fabrication of depletion-mode GaAs MOSFET, a new planarized trench isolation technique for GaAs MOSFET''s fabrication by the LPCEO method has been proposed. The LPCEO-trench-isolation technique can be operated at low temperature with a simple and low-cost process. As compared with conventional mesa isolation, the LPCEO-trench-isolation can provide fairly good planarity and electrical results to isolate the active region of GaAs devices. In addition, we demonstrate GaAs MOSFET with planarized trench isolation and selective oxidized gate both by the LPCEO method. The fabricated GaAs MOSFET exhibits current-voltage characteristics with complete pinch-off and saturation characteristics.

Content
Abstracts i
Acknowledgements vi
List of Tables x
List of Figures xi
Chapter 1 Introduction 1
1.1 Background …………………………………………………………1
1.2 Organization …………………………………………………………4
Chapter 2 Preparation and characterization of
LPCEO-oxide film 7
2.1 Introduction …………………………………………………………7
2.2 Oxidation procedures of LPCEO method …………………………8
2.3 Physical properties of TEM image ………………………………15
2.4 Physical properties of AFM image ……………………………17
2.5 Chemical properties of XPS results …………………………17
2.6 Electrical properties ……………………………………………22
2.6.1 Current-Voltage characteristics ……………………………22
2.6.2 Dielectric strength ……………………………………………24
2.6.3 Capacitance-Voltage characteristics ………………………24
2.6.4 High-frequency capacitance method …………………………30
2.7 Summary ………………………………………………………………31
Chapter 3 Fabrication processes of the GaAs MOSFET
using LPCEO method 36
3.1 Introduction ………………………………………………………36
3.2 Device structure …………………………………………………37
3.3 GaAs MOSFET with conventional LPCEO process ……………37
3.4 GaAs MOSFET with PR-SLPCEO process …………………………41
3.5 GaAs MOSFET with novel M-SLPCEO process ……………………45
3.6 Summary ………………………………………………………………47
Chapter 4 The dc and microwave performance
of GaAs MOSFET 51
4.1 Introduction ………………………………………………………51
4.2 The dc characteristics …………………………………………52
4.2.1 Effects of device geometric size of gate length ……53
4.2.2 Effects of gate oxide thickness …………………………58
4.3 The microwave characteristics of fT and fmax ……………66
4.3.1 Effects of device geometric size of gate length ………70
4.3.2 Effects of gate oxide thickness ……………………………76
4.4 The noise performance ……………………………………………79
4.5 Summary ………………………………………………………………91
Chapter 5 Temperature effects on the device performances
of GaAs MOSFET 92
5.1 Introduction ………………………………………………………92
5.2 The gate leakage current of GaAs MOSFET …………………93
5.2.1 Carrier transport mechanism …………………………………93
5.2.2 Effect of operating temperature ……………………………95
5.2.3 The reliability of gate oxide film ………………………97
5.3 The temperature effect on dc characteristic of GaAs MOSFET …………………………………………………………………………101
5.4 The temperature effect on microwave characteristic of GaAs MOSFET ……………………………………………………………………107
5.5 The reliability of the GaAs MOSFET …………………………116
5.6 Summary ……………………………………………………………119
Chapter 6 Application of LPCEO method 120
6.1 Introduction ……………………………………………………120
6.2 LPCEO-trench-isolation …………………………………………121
6.3 GaAs MOSFET with LPCEO-trench-isolation …………………126
6.4 Summary ……………………………………………………………129
Chapter 7 Conclusions 131
7.1 Conclusions ………………………………………………………131
7.2 Future works ……………………………………………………132
References ……………………………………………………………134
Publication List 143
Vita 145

[1] R. Williams, ch.1, Boston London: Artech House, 1990.
[2] R. Williams, New York: Plenum, 1989.
[3] M. J. Jeng, J. G. Hwu, IEEE. Election. Dev. Lett., vol.17, p.575, 1996.
[4] D. J. Coleman, D. W. Shaw, and R. D. Dobrott, J. Electrochem. Soc., vol.124, p.239, 1977.
[5] R. Nakamura and H. Ikoma, , Jpn. J. Appl. Phys. Pt.2, vol. 35, p. L8, 1996.
[6] P. A. Bertrand, J. Electrochem. Soc., vol. 132, p. 973, 1985.
[7] T. Sawada, H. Hasegawa, and H. Ohno, Jpn. J. Appl. Phys., vol. 26, no. 11, p. L1871, 1987.
[8] C. P. Ho, J. D. Plummer, J. D. Meindl, and B. E. Deal, J. Electrochem. Soc., vol. 125, p. 665, 1978.
[9] B. E. Deal and M. Sklar, J. Electrochem. Soc., vol. 112, p. 430, 1965.
[10] I. Shiota, N. Miyamoto, and J. ichi Nishizawa, J. Electrochem. Soc., vol. 124, p. 1405, 1977.
[11] B. E. Deal, J. Electrochem. Soc., vol. 125, p. 576, 1978.
[12] M. Passlack, M. Hong, E. F. Schubert, J. R. Gwo, J. P. Mannaerts, S. N. G. Chu, N. Moriya, and F. A. Thiel, Appl. Phys. Lett., vol. 66, no. 5, p. 625, 1995.
[13] M. Passlack, M. Hong, J. P. Mannaerts, R. L. Opila, S. N. G. Chu, N. Moriya, F. Ren, and J. R. Gwo, IEEE Tr. on Electron Devices, vol. 66, no. 5, p. 625, 1995.
[14] M. Passlack, M. Hong, and J. P. Mannaerts, Appl. Phys. Lett., vol. 68, p. 1099, 1996.
[15] K. Maezawa, T. Mizutani, K. Arai, and F. Yanagawa, IEEE Electron Device Letters, vol. EDL-7, no. 7, p. 454, 1986.
[16] S. Fujita, M. Hirano, K. Maezawa, and T. Mizutani, IEEE Electron Device Letters , vol. EDL-8, no. 5, p. 226, 1987.
[17] E. F. Yu, J. Shen, M. Walther, T. C. Lee, and R. Zhang, Electronics Letters, vol. 36, p. 359, 2000.
[18] K. D. Choquette, K. M. Geib, C. I. H. Ashby, R. D. Twesten, O. Blum, H. Q. Hou, D. M. Follstaedt, B. E. Hammons, D. Mathes, and R. Hull, IEEE J. Selected Topic in Quantum Electron., vol. 3, no. 3, p. 916, 1997.
[19] N. Basu and K. N. Bhat, J. Appl. Phys., vol. 63, p. 5500, 1988.
[20] C. W. Wilmsen, P. D. Kirchner, J. M. Baker, D. T. Mclnturff, G. D. Pettit, and J. M. Wooldall, J. Vac. Sci. and Technol. B, vol. 6, p. 1180, 1988.
[21] E. Ettedgui, K. T. Park, J. Cao, Y. Gao, and M. W. Ruckman, J. Appl. Phys., vol. 77, p. 5411, 1995.
[22] P. Schmuki, G. I. Sproule, J. A. Bardwell, Z. H. Lu, and M. J. Graham, J. Appl. Phys., vol. 79, p. 7303, 1996.
[23] F. Ren, M. Hong, W. S. Hobson, J. M. Kuo, J. R. Lothian, J. P. Mannaerts, J. Kwo, S. N. G. Chu, Y. K. Chen, and A. Y. Cho, Solid-State Electron , vol. 41, no. 11, p. 1751, 1997.
[24] Y. C. Wang, M. Hong, J. M. Kuo, J. P. Mannaerts, J. Kwo, H. S. Tsai, J. J. Krajewski, Y. K. Chen, and A. Y. Cho, IEEE Electron Device Lellers , vol. 20, no. 9, p. 457, 1999.
[25] M. Passlack, M. Hong, and J. P. Mannaerts, Solid-State Electronics., vol. 39, no. 8, p. 1133, 1996.
[26] M. P. Houng, C. J. Huang, Y. H. Wang, N. F. Wang, and W. J. Chang, J. Appl. Phys., vol. 82, no. 11, p. 5788, 1997.
[27] C. J. Huang, M. P. Houng, Y. H. Wang, and H. H. Wang, J. Appl. Phys., vol. 86, no. 12, p. 7151, 1999.
[28] H. H. Wang, Y. H. Wang, and M. P. Houng, Jpn. J. Appl. Phys. Pt.2 , vol. 37, no. 8B, p. L988, 1998.
[29] J. Y. Wu, H. H. Wang, Y. H. Wang, and M. P. Houng, IEEE Transactions on Electron Devices , vol. 48, no. 4, p. 634, 2001.
[30] J. Y. Wu, H. H. Wang, Y. H. Wang, and M. P. Houng, IEEE Electron Device Letters , vol. 20, p. 18, 1999.
[31] J. Y. Wu, H. H. Wang, Y. H. Wang, and M. P. Houng, IEEE Electron Device Letters , vol. 22, p. 2, 2001.
[32] S. K. Ghandhi, ch. 7. New York: John Wiley & Sons, Inc., 1994.
[33] C. W. Wilmsen, ed., ch. 7. New York: Plenum Press, 1985.
[34] S. P. Murarka, Appl. Phys. Lett., vol. 26, p. 180, 1975.
[35] D. N. Butcher and B. J. Sealy, J. Phys. D: Appl. Phys., vol. 11, p. 1451, 1978.
[36] H. T. Minden, J. Electrochem. Soc. , vol. 109, no. 8, p. 733, 1962.
[37] D. N. Butcher and B. J. Sealy, Electron. Lett., vol. 13, no. 19, p. 558, 1977.
[38] H. Takagi, G. Kano, and I. Teramoto, J. Electrochem. Soc., vol. 125, p. 579, 1978.
[39] I. Teramoto, H. Takagi, and G. Kano, Jpn. J. Appl. Phys., vol. 18, no. 4, p. 723, 1979.
[40] T. H. Oh, D. L. Huffaker, L. A. Graham, H. Deng, and D. G. Deppe, Electron. Lett., vol. 32, no. 21, p. 2024, 1996.
[41] S. Iida and K. Ito, J. Electrochem. Soc., vol. 118, p. 768, 1971.
[42] S. K. Ghandhi, ch. 9. New York: John Wiley & Sons, Inc., 1994.
[43] D. E. Aspnes and A. A. Studna, Appl. Phys. Lett, vol. 46, no. 11, p. 1071, 1985.
[44] S. Osakabe and S. Adachi, J. Electrochem. Soc., vol. 144, no. 1, p. 290, 1997.
[45] C. C. Chang, P. H. Citrin, and B. Schwartz, J. Vac. Sci. Technol., vol. 14, no. 4, p. 943, 1977.
[46] R. Meyer-Arendt, Englewood Cliffs, N.J.: Prentice-Hall Inc., 1971.
[47] T. Sugano, J. Electrochem. Soc., vol. 121, no. 1, p. 113, 1974.
[48] S. M. Sze, ed., ch. 3. New York: McGraw-Hill Book Co., 1988.
[49] H. H. Wang, J. Y. Wu, Y. H. Wang, and M. P. Houng, J. Electrochem. Soc., vol. 146, no. 6, p. 2328, 1999.
[50] C. D. Thurmond, G. P. Schwartz, G. W. Kammlott, and B. Schwartz, J. Eletrochem. Soc., vol. 127, p. 1366, 1980.
[51] G. P. Schwartz, G. J. Gualtieri, G. W. Kammoltt, and B. Schwartz, J. Electrochem. Soc., vol. 126, p. 1737, 1979.
[52] T. Ishikawa and H. Ikoma, Jpn. J. Appl. Phys. Pt.1, vol. 31, p. 3981, 1992.
[53] C. M. Demanet and M. A. Marais, Surface and interface analysis, vol. 7, no. 1, p. 13, 1985.
[54] B. Schwartz, J. Electrochem. Soc., vol. 118, p. 657, 1971.
[55] B. Schwartz, S. E. Haszko, and D. R. Wonsidler, J. Electrochem. Soc., vol. 118, p. 1229, 1971.
[56] Z. Liliental-Weber, C. W. Wilmsen, K. M. Geib, P. D. Kirchner, J. M. Baker, and J. M. Woodall, J. Appl. Phys., vol. 67, p. 1863, 1990.
[57] P. D. Kirchner, A. C. Warren, J. M. Wooldall, C. W. Wilmsen, S. L. Wright, and J. M. Baker, J. Electrochem. Soc., vol. 135, p. 1822, 1988.
[58] D. R. Lide, ed., ch. 4. Boca Raton, Florida: CRC press, 1997.
[59] M. Passlack, E. F. Schubert, W. S. Hobson, M. Hong, N. Moriya, S. N. G. Chu, K. Konstadinidis, J. P. Mannaerts, M. L. Schnoes, and G. L. Zydzik, J. Appl. Phys., vol. 77, p. 686, 1995.
[60] C. W. Wilmsen, ed., ch. 3. New York: Plenum Press, 1985.
[61] Y. H. Jeong, K. H. Choi, and S. K. Jo, ''IEEE Electron Device Letters, vol. 15, p. 251, 1994.
[62] E. H. Nicollian and J. R. Brews, ch. 2,3,4. New Jersey: Artech House, 1982.
[63] E. H. Nicollian and J. R. Brews, ch. 8. New Jersey: Artech House, 1982.
[64] H. Takagi, G. Kano, and I. Teramoto, IEEE Trans. Electron Devices, vol. ED-25, p. 551, 1978.
[65] D. L. Lile, A. R. Clawson, and D. A. Collins, Appl. Phys. Lett., vol. 29, no. 3, p. 207, 1976.
[66] T. Mimura, N. Yokoyama, Y. Nakayama, and M. Fukuta, Dig. Tech. Papers, p. 47, 1977.
[67] M. Hong, F. Ren, J. M. Kuo, W. S. Hobson, J. Kwo, J. P. Mannaerts, J. R. Lothian, and Y. K. Chen, J. Vac. Sci. Technol. B, vol. 16, no. 3, p. 1395, 1998.
[68] R. Williams, ch. 2. Boston London: Artech House, 1990.
[69] H. H. Wang, C. J. Huang, Y. H. Wang, and M. P. Houng, Jpn. J. Appl. Phys. Pt.2, vol. 37, no. 1A/B, p. L67, 1998.
[70] H. H. Wang, D. W. Chou, Y. H. Wang, and M. P. Houng, Physica Scripta, vol. T79, p. 239, 1999.
[71] H. H. Wang, D. W. Chou, J. Y. Wu, , Y. H. Wang, and M. P. Houng, J. Applied Phys., vol. 87, p. 2629, MARCH 2000.
[72] R. Williams, ch. 4. Boston London: Artech House, 1990.
[73] R. Williams, ch. 6. Boston London: Artech House, 1990.
[74] R. Williams, ch. 5. Boston London: Artech House, 1990.
[75] R. Williams, ch. 11. Boston London: Artech House, 1990.
[76] M. Heiblum, M. I. Nathan, and C. A. Chang, Solid State Electronics, vol. 25, no. 3, p. 1855, 1982.
[77] R. Williams, ch. 3. Boston London: Artech House, 1990.
[78] J. M. Golio, ch. 1. Boston: Artech House, 1991.
[79] A. Moschwitzer, ch. 2. New York: Oxford, 1991.
[80] R. Williams, ch. 17. Boston London: Artech House, 1990.
[81] H. L. Hartnagel, ch. 2. New York: John Wiley \& Sons, 1991.
[82] F. M. Klaassen, Process and Device Modeling for Integrated Design, p. 541, 1977.
[83] D. K. Schrdoder, ch. 4. New York: John Wiley \& Sons, 1990.
[84] C. L. Lau, M. Feng, T. R. Lepkowski, G. W. Wang, Y. Chang, and C. Ito, IEEE Electron Device Letters, vol. 10, p. 409, September 1989.
[85] M. Feng, H. Kanber, V. K. Eu, E. Watkins, and L. R. Hackett, Appl. Phys. Lett., vol. 44, p. 231, 1984.
[86] I. Banerjee, P. W. Chye, and P. E. Gregory, IEEE Electron Device Letters, vol. 9, p. 10, 1988.
[87] R. Q. Lane, Proc. IEEE, p. 1461, 1969.
[88] L. Escotte, F. Srederic, and J. Graffeuil, ''IEEE Transactions on Instrumentation and Measurement, vol. 43, p. 536, 1994.
[89] G. Dambrine, J. P. Raskin, F. Danneville, D. V. Janvier, J. P. Colinge, and A. Cappy, ''IEEE Transactions on Electron Devices,vol. 46, p. 1733, 1999.
[90] C. E. Biber, M. L. Schmatz, T. Morf, U. Lott, E. Morifuji, and W. Bachtold, IEEE MTT-S Digest, vol. TU3A-3, p. 145, 1998.
[91] C. Y. Su, L. P. Chang, G. W. Huang, Y. P. Ho, B. M. Deng, C. L. Chen, L. Y. Leu, K. A. Wen, and C. Y. Chang, Electron. Lett., vol. 36, p. 1280, 2000.
[92] M. J. Deen and C. H. Chen, Proc. IEEE Int. Conf. On Microelectronic Test Structures, vol. 12, p. 34, 1999.
[93] F. S. Shoucair and P. K. Ojala, IEEE Transactions on Electron Devices, vol. 39, p. 1551, 1992.
[94] C. Ito, T. Jenkins, G. Trombley, R. Lee, R. Reston, C. Havasy, B. Johnson, and C. Eppers, IEEE Electron Device Letters, vol. 17, p. 16, 1996.
[95] R. Lee, G. Trombley, B. Johnson, R. Reston, M. Mah, C. Havasy, and C. Ito, IEEE Electron Device Letters, vol. 16, p. 265, 1995.
[96] E. F. Runnion, S. M. Gladstone, IV, R. S. Scott, Jr., D. J. Dumin, S. L. Lie, Member, J. C. Mitros, IEEE Transactions on Electron Devices, vol. 44, p. 993, 1997.
[97] J. Kolodzey, S. Member, IEEE, E. A. Chowdhury, T. N. Adam, G. Qui, I. Rau, J. O. Olowolafe, J. S. Suehle, S. Member, IEEE, and Y. Chen, IEEE Transactions on Electron Devices, vol. 47, p. 121, 2000.
[98] D. J. Dumin and J. R. Maddux, IEEE Transactions on Electron Devices, vol. 40, p. 986, 1993.
[99] S. M. Sze, New York: John Wiley & Sons, Inc., 1981.
[100] P. Olivo, T. N. Nguyen, and B. Ricco, IEEE Transactions on Electron Devices, vol. 35, p. 2259, 1988.
[101] H. Becke, R. Hall, and J. White, Solid-State Electronics, vol. 8, p. 813, 1965.
[102] U. Schwalke, Z. Gabric, N. Elbel, K. Bothe, D. Hadawi, I. Janssen, P. Schon, A. Inioutis, R. Klose, and J. Plagmann, IEEE Electron Device Letters, vol. 20, p. 563, 1999.
[103] R. Bashir and F. Hebert, IEEE Electron Device Letters, vol. 17, p. 352, 1996.
[104] S. H. Pyi, I. S. Yeo, D. H. Weon, Y. B. Kim, and S. K. Lee, IEEE Electron Device Letters, vol. 20, p. 384, 1999.
[105] T. E. Kazior, J. Electrochem. Soc., vol. 137, p. 2257, 1990.
[106] K. Billen, M. J. Kelly, D. Lancefield, R. M. Gwilliam, D. A. Ritchie, S. Gumer, G. A. C. Jones, E. H. Linfield, and A. P. Churchill, Electron. Lett., vol. 30, p. 1359, 1994.
[107] D. C. D''Avanzo, IEEE Tr. Microwave Theory and Techniques, vol. MTT-30, p. 955, 1982.
[108] K. T. Short and S. J. Pearton, J. Electrochem. Soc., vol. 135, p. 2835,1988.
[109] S. J. Pearton, F. Ren, J. R. Lothian, T. R. Fullowan, A. Katz, P. W. Wisk, R. G. Elliman, M. C. Rigdway, C. Jagadish, and J. S. Williams, 'J. Appl. Phys., vol. 71, p. 4949,1992.
[110] F. Clauwaert, P. V. Daele, R. Baets, and P. Lagasse, J. Electrochem. Soc., vol. 134, p. 711, 1987.
[111] J. P. de Souza, I. Danilov, and H. Boudinov, J. Appl. Phys., vol. 84, p. 4757, 1998.
[112] D. W. Chou, R. F. Lou, H. H. Wang, Y. H. Wang, and M. P. Houng, Jpn. J. Appl. Phys., 2000.
[113] E. Yablonovitch, C. J. Sandroff, R. Bhat, and T. Gmitter, Appl. Phys. Lett., vol. 51, p. 4391, 1987.
[114] H. H. Lee, R. J. Racicot, and S. H. Lee, Appl. Phys. Lett., vol. 54, p. 724--726, 1989.
[115] H. C. Ko, K. Uchida, and S. Nakatsuka, Jpn. J. Appl. Phys. Pt.2, vol. 33, p. L297, 1994.