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研究生:陳育儒
研究生(外文):Yu-Ju Chen
論文名稱:3維晶方尺寸構裝之尺寸效應的數值探討
論文名稱(外文):A Numerical Investigation of Scale Effects for 3D CSP
指導教授:周榮華周榮華引用關係
指導教授(外文):Jung-Hua Chou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:工程科學系碩博士班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:114
中文關鍵詞:熱循環測試疲勞壽命三維晶方尺寸構裝
外文關鍵詞:thermal cyclic loading3D CSPvon Mises stressfatigue lifesteady-state creep constitutive law
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本研究選用Sharp所推出之CSP、stacked CSP和triple-chip stacked CSP三種封裝體作為分析之模型的依據,利用ANSYS進行模擬分析,以了解不同封裝體在經過熱循環測試後,chip thickness 、substrate thickness、substrate material和die attach thickness等因素對其晶片所承受之應力和封裝體疲勞壽命之影響。
分析結果發現,三種封裝體中,以CSP的疲勞壽命最高,約2494cycles,而以triple-chip stacked CSP之晶片承受最大的von Mises stress,約180Mpa。當substrate material為PI時,其疲勞壽命皆高於FR-4和BT,且三種封裝體之晶片也承受最大的von Mises stress,約180Mpa。隨著die attach thickness和substrate thickness的增加或chip thickness的減少,皆可有效的提高封裝體的疲勞壽命,其中以substrate thickness的影響最為明顯,其厚度從0.12mm增加至0.36mm時,triple-chip stacked CSP之疲勞壽命從1935cycles提高為321656cycles。此外,在三封裝體承受熱循環測試後,以CSP之晶片所承受之von Mises stress受substrate thickness影響最為明顯,從134Mpa增加至180Mpa,約提高34%。
A numerical investigation of the scale effects for 3D CSP, including single CSP, stacked CSP and triple-chip stacked CSP, subjected to thermal cyclic loading is presented. The emphasis is on the effects of die attach thickness, substrate thickness, substrate material and chip thickness on the fatigue life of these packages. In addition, the variation of von Mises stress in chips is also investigated. The Sn62Pb36Ag2 solder balls are assumed to obey the Garofalo-Arrhenius steady-state creep constitutive law. The temperature applied to these packages with the PCB assembly ranges from -20℃~110℃.There are a total of three cycles.
Computational results indicate that the fatigue life of single CSP is highest among these packages and the maximum von Mises stress for chips occurs in triple-chip stacked CSP. It is observed that the die attach thickness, substrate material and chip thickness have significant influence on the fatigue life of these packages. Among these factors, the substrate thickness has a larger impact. With the change of substrate thickness from 0.12 mm to 0.36 mm, the fatigue life of triple-chip stacked CSP increases greatly from 1935 cycles to 321656 cycles. Besides, it is found that von Mises stress in chips is also affected by many factors such as die attach thickness, chip thickness and so on. For the range of substrate thickness is studied, von Mises stress in the chip of single CSP increases significantly from 134 Mpa to 180 Mpa.
目 錄
目錄 I
表目錄 IV
圖目錄 V
符號說明 XII

第一章、導論 1
前言 1
1-1 3D封裝技術之簡介 1
1-2 Triple-chip stacked CSP之概述[16] 8
1-3 研究動機 10

第二章、ANSYS概論 12
前言 12
2-1 ANSYS內容之簡介 12
2-1-1 前處理 12
2-1-2 運算處理 14
2-1-3 後處理 15
2-2 懸臂樑數值分析 16
2-2-1 3D元素之簡介 16
2-2-2 懸臂樑模擬及結果探討 17

第三章、數值模型及基本假設 20
前言 20
3-1 數值模型說明 20
3-2 材料性質設定 23
3-3 邊界條件 25
3-4 溫度負載 25
3-5 疲勞壽命預測 26

第四章、結果與討論 28
前言 28
4-1 CSP、stacked CSP及triple-chip stacked CSP分析結果之探討 29
4-2 Die attach thickness對CSP、stacked CSP及triple-chip stacked CSP之影響 34
4-3 Substrate thickness對CSP、stacked CSP及triple-chip stacked CSP之影響 37
4-4 Substrate material對CSP、stacked CSP及triple-chip stacked CSP之影響 41
4-5 Chip thickness對CSP、stacked CSP及triple-chip stacked CSP之影響 44

第五章、結論 46

參考文獻 50
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