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研究生:許修豪
研究生(外文):Hsiu-Hao Hsu
論文名稱:在熱循環下晶圓級晶片尺寸構裝可靠度分析
論文名稱(外文):Reliability of the WLCSP Subjected by the Thermal Cycle
指導教授:黃明哲黃明哲引用關係
指導教授(外文):Ming-Jer Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:工程科學系碩博士班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:67
中文關鍵詞:構裝熱循環晶圓級可靠度
外文關鍵詞:ReliabilitypackagingWLCSPthermal cycle
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本文針對晶圓級晶片尺寸構裝(WLCSP)在環境溫度熱循環測試下,利用ANSYS有限元素分析軟體模擬WLCSP構裝體之材料非線性結構行為,以探討焊錫接點在各種不同的FR-4板設計之下對焊錫接點可靠度的影響。
由本文研究結果顯示,由於受到構裝材料性質差異之影響,使得構裝體在受到熱循環作用之下產生變形,並在焊錫接點外側角落產生最大等效應變,使得構裝體最外側焊錫接點與黏著墊接合處會造成疲勞破壞。針對本文所設計之基板模型在製程上省略了微貫孔樹脂增層基板重新佈線之問題;以結構分析而言,與樹脂增層基板比較之結果發現,此基板模型可降低整體構裝之位移量、最外側焊錫接點之等效應力、塑性剪應變範圍並增加其可靠度,且避免了焊錫接點下方與黏著墊發生脫離的可能。最後,以3-D模型探討在2-D平面應力分析時所會忽略掉的結果。
本文考慮焊錫接點黏塑性材料之潛變效應,以ANSYS有限元素軟體進行分析,改變WLCSP晶片與基板組裝上之設計,以提高其焊錫接點之疲勞壽命,作為WLCSP構裝體在設計組裝上之參考。
摘要…………………………………………………………………I
誌謝…………………………………………………………………II
目錄…………………………………………………………………III
表目錄………………………………………………………………VI
圖目錄………………………………………………………………VII
符號說明……………………………………………………………XI
第一章 緒論………………………………………………………1
前言……………………………………………………………1
1-1 研究動機與目的…………………………………………… 1
1-2 文獻回顧…………………………………………………… 2
第二章 覆晶構裝及WLCSP簡介………………………………… 5
前言…………………………………………………………………5
2-1 覆晶構裝…………………………………………………… 6
2-1-1 覆晶構裝簡介…………………………………………… 6
2-1-2 覆晶構裝製程…………………………………………… 7
2-2 WLCSP……………………………………………………8
2-2-1 WLCSP簡介………………………………………8
2-2-2 WLCSP重配置及長凸塊過程………………………………9
2-2-3 WLCSP之組裝……………………………………11
第三章 模型假設…………………………………………………12
前言…………………………………………………………………12
3-1 結構尺寸…………………………………………………… 12
3-1-1 含微貫孔樹脂增層之基板模型………………………… 13
3-1-2 直接挖孔樹脂增層基板………………………………… 13
3-1-3 3-D模型……………………………………………………14
3-2 材料特性…………………………………………………… 15
3-3 邊界條件與負載……………………………………… 16
3-4 分析方法…………………………………………………… 17
3-4-1 前處理…………………………………………………… 18
3-4-2 解答模組………………………………………………… 18
3-4-3 後處理…………………………………………………… 19
第四章 結果與討論………………………………………………20
前言…………………………………………………………………20
4-1 WLCSP組裝之位移變形………………………………………20
4-1-1 整體構裝體之變形……………………………………… 20
4-1-2 最外側焊錫接點之變形………………………………… 21
4-2 WLCSP組裝之應力與應變……………………………………21
4-2-1 等效應力………………………………………………… 21
4-2-2 等效應變………………………………………………… 22
4-2-3 磁滯循環、剪應力與剪應變…………………………… 23
4-3 2-D與3-D之分析比較……………………………………… 23
4-3-1 位移、等效應力與應變………………………………… 24
4-3-2 磁滯循環、剪應力與剪應變…………………………… 24
第五章 結論與未來研究方向……………………………………26
5-1 結論………………………………………………………… 26
5-2 未來研究方向……………………………………………… 27
參考文獻……………………………………………………………28
附錄A Anand’s Model……………………………………… 64
附錄B 可靠度理論…………………………………………… 66
1.J. H. Lau, “Critical Issues of Wafer Level Chip Scale Package (WLCSP) with Emphasis on Cost Analysis and Solder Joint Reliability,” IEEE/CPMT Int’l Electronics Manufacturing Technology Symposium, pp.33-45, 2000.

2.H. L. J. Pang and T. I. Tan, G. Y. Lim and C. L. Wong, “Thermal Stress Analysis of Direct Chip Attach Electronic Packaging Assembly,” IEEE Electronic Packaging Technology Conference, pp. 170-176, 1997.

3.J. Wang, Z. Qian, D. Zou, and S. Liu, “Creep Behavior of a Flip-Chip Package by Both Fem Modeling and Real Time Moire’ Interferometry,” Transactions of the ASME Journal of Electronic Packaging, Vol. 120, pp. 179-185, June 1998.

4.S. Rzepka, M. A. Korhonen, E. Meusel, “The Effect of Underfill and Underfill Delamination on the Thermal Stress in Flip-Chip Solder Joints,” Transactions of the ASME, Journal of Electronic Packaging, Vol. 120, December 1998.

5.E. Madenci, S. Shkarayev, and R. Mahajan, “Potential Failure Sites in a Flip-Chip Package with and without Underfill,” Transactions of the ASME Journal of Electronic Packaging, Vol. 120, pp. 336-341, December 1998.

6.Stelios Michaelides and Suresh K. Sitaraman, “Effect of Material and Geometry Parameters on the Thermo-Mechanical Reliability of Flip-Chip Assemblies,” IEEE InterSociety Conference on Thermal Phenomena, pp. 193-200, 1998.

7.Goh, and Teck Joo, “Parametric Finite Element Analysis of Solder Joint Reliability of Flip Chip on Board,” IEEE/CPMT Electronics Packaging Technology Conference, pp. 57-62, 1998.

8.K. H. Teo, “Reliability Assessment of Flip Chip on Board Connection,” IEEE/CPMT Electronics Packaging Technology Conference, pp. 269-273, 1998.

9.John Lau and Chris Cang, “Solder Joint Crack Propagation Analysis of Wafer-Level Chip Scale Package on Printed Circuit Board Assemblies,” IEEE Electronic Components and Technology Conference, pp. 1360-1368, 2000.

10.J. H. Lau, S.-W. R. Lee and C. Chang, “Effects of Underfill Material Properties on the Reliability of Solder Bumped Flip Chip on Board with Imperfect Underfill Encapsulants,” IEEE Transactions on Components and Packaging Technologies, Vol. 23, No. 2, pp. 323-333, June 2000.

11.J. H. Lau and S.-W. R. Lee, ”Reliability of Wafer Level Chip Scale Package (WLCSP) with 96.5Sn-3.5Ag Lead-Free Solder Joints on Build-UP Microvia Printed Circuit Board,” IEEE International Symposium Electronic Material and Packaging, pp. 55-63, 2000.

12.J. H. Lau, S. H. Pan, and C. Chang, ”Creep Analysis of Solder Bumped Direct Chip Attach (DCA) on Microvia Build-UP Printed Circuit Board with Underfill,” IEEE International Symposium Electronic Material and Packaging, pp. 115-126, 2000.

13.J. H. Lau and S.-W. R. Lee, “Effects of Build-Up Printed Circuit Board Thickness on the Solder Joint Reliability of a Wafer Level Chip Scale Package (WLCSP),” IEEE International Symposium Electronic Material and Packaging, pp. 127-135, 2000.

14.R. Darveaux, “Solder Joint Fatigue Life Model,” in Design and Reliability of Solders and Solder Interconnections, The Minerals, Metals and Materials Society (TMS) , pp. 213-218,1997.

15.W. Engelmaier, “Fatigue Life of Leadless Chip Carrier Solder Joints During Power Cycling,” IEEE Transactions on Components, Hybrids and Manufacturing Technology, Vol. CHMT-6, No3, pp. 52-57,1983.

16.J. H. Lau, and S. W. R. Lee, Chip Scale Package, Design, Materials, Process, Reliability, and Applications, McGraw-Hill, New York, 1999.

17.J. H. Lau, and S. W. R. Lee, Low Cost Flip Chip Technologies, for DCA, WLASP, and PBGA Assemblies, McGraw-Hill, New York, 2000.

18.J. H. Lau, and S. W. R. Lee, Microvias, for Low Cost High Density Interconnect, McGraw-Hill, New York, 2001.

19.J. H. Lau, and S. W. R. Lee, Electronic Packaging, Design, Materials, Process, and Reliability, McGraw-Hill, New York, 1998.
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