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研究生:陳和良
研究生(外文):Ho-Liang Chen
論文名稱:模數乘法演算法運用於智慧卡之研究
論文名稱(外文):Study on Modular Multiplication Algorithms for Smart Card Applications
指導教授:侯廷偉侯廷偉引用關係
指導教授(外文):Ting-Wei Hou
學位類別:碩士
校院名稱:國立成功大學
系所名稱:工程科學系專班
學門:工程學門
學類:綜合工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:41
中文關鍵詞:模數乘法智慧卡
外文關鍵詞:Modular MultiplicationSmart Card
相關次數:
  • 被引用被引用:1
  • 點閱點閱:483
  • 評分評分:
  • 下載下載:82
  • 收藏至我的研究室書目清單書目收藏:3
目前大部份使用中的公開金鑰密碼系統中,最消耗時間及系統資源的部份就是modular exponentiation ,而其基礎則在於modular multiplication。本研究的目的在於儘可能地降低在smart card 上所須耗用的資源,特別是以可行的演算法來避免使用硬體除法器,藉此在標準微處理器上實作公開金鑰密碼演算法。
研究內容將詳細探討Montgomery modular multiplication algorithm在reduction過程中估算除法商數的演算法的實作方式。在考慮到以C++或Pascal等高階語言無法有效率地處理多重精確度的算術運算(主要是有關標準算術運算中carries 的取得及對記憶體的存取速度),實作中將以硬體描述語言來完成Montgomery algorithm的設計。
In most public-key crypto systems used today, the most time consuming part of these systems is the modular exponentiation. The base of this computation is the modular multiplication. Our study is to minimize the resources used in smart card. Hardware divisors will be prohibited if a comparable efficiency is obtained without it. Our study also focuses on the ability to implement modular multiplication algorithm on nearly standard processor.
This article first shows the implementation of the reduction of the Montgomery modular multiplication algorithm. On concerning the drawback on dealing with multiprecision arithmetic by high-level languages such as C++ or Pascal, the implementation will be finished by Verilog hardware description language on the design of Montgomery algorithm.
中 文 摘 要 i
Abstract ii
誌謝 iii
章 節 目 錄 iv
圖目錄 vi
第一章 RSA密碼系統簡介 1
1-1 模數運算 1
1-2 RSA 演算法 3
第二章 模數乘法運算 4
2-1 Notations 4
2-2 Interleaved multiplications-reductions 4
2-3 Residue number systems 5
第三章 多精確度的整數運算 7
3-1 Addition and Subtraction 7
3-2 Multiplication 8
3-3 Squaring 9
3-4 Extended Euclidean algorithm 9
3-5 Binary extended gcd algorithm 10
第四章 以Montgomery Algorithm實作模數乘法運算 12
4-1 Montgomery reduction 12
4-2 Montgomery multiplication 14
第五章 以硬體描述語言實作Montgomery Algorithm 17
5-1 VHSIC Hardware Description Language 17
5-2 Verilog Hardware Description Language 19
5-3 Wave form simulations 21
第六章 結論 27
參考索引 28
附錄 30
自述 41
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division,” Mathematics of Computation, Vol. 44, pp. 519 –
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of Montgomery multiplication algorithm,” IEEE Trans.
Compt., Vol. 42, no 6, pp. 693, 1993
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EUROCRYPT ’90, Vol. 473, pp. 51-60, 1991
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obtaining digital signatures and public key cryptosystems,”
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[Ckim01] Chinuk Kim ,“Vhdl Implementation Of Systolic Modular
Multiplications On RSA Cryptosystem ,“ 2001
[Knuth98] D.E. Knuth , ”The Art of Computer Programming, Volume
2, Seminumerical Algorithms .Addison-Wesley, Reading,
MA Third edition,1998
[MSJV93] M. Shand and J. Vuillemin, “Fast Implementations of RSA
cryptography," Proceedings of the 11th IEEE Symposium
on Computer Arithmetic, IEEE Computer Society Press,
Los Alamitos, CA, 1993, pp. 252-259.
[CDW92] C.D. Walter, “Faster modular multiplication by operand
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[PJA96] Peter J. Ashenden, “The Designers’ guide to VHDL,”
Morgan Kaufmann Publishers, Inc. pp.351, Netherlands,
1996
[黃文吉02]黃文吉, “VHDL 基本程式寫作及應用”, 儒林圖書公司,
Feb 2002
[鄭信源02]鄭信源, “Verilog 硬體描述語言數位電路設計實務”, 儒
林圖書公司, Feb 2002
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