跳到主要內容

臺灣博碩士論文加值系統

(54.224.133.198) 您好!臺灣時間:2022/01/27 05:24
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:曹志彬
研究生(外文):Chih-Pin Tsao
論文名稱:深次微米元件熱載子效應
論文名稱(外文):Hot-Carrier reliability in deep submicron CMOS device
指導教授:陳志方
指導教授(外文):Jone F. Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:微電子工程研究所碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:77
中文關鍵詞:熱載子
外文關鍵詞:hot-carrier
相關次數:
  • 被引用被引用:1
  • 點閱點閱:286
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
本篇論文主要的目的是研究深次微米元件之熱載子可靠度。將藉由與業界的合作,取得現今產業界先進的0.18μm及0.15μm製程技術元件,進一步探討元件縮小化對元件可靠度的影響。
隨著製程技術的演進,元件縮小化的優點,儘管諸如元件密集度上升、成本的下降及元件擁有較大的驅動電流等。但隨之而來的超薄氧化層所造成的漏電流效應及短通道效應,卻在可靠度方面產生嚴重的問題。以0.18μm及0.15μm製程技術元件為例,通道長度已縮小至(0.18μm及0.15μm),而閘極氧化層也在20∼50Å左右,此時元件的熱載子效應是否仍符合長通道元件所預期一般,及超薄氧化層所造成的漏電流效應,對元件可靠度的影響,都是值得注意的問題。
本篇論文將分四大章節討論。第一章將簡要的介紹何謂熱載子效應。一些關於熱載子效應的相關基本資料及概述將在此章節中一一介紹。第二章主要是探討nMOSFET深次微米元件熱載子效應的影響。研究發現,當製程技術演進至0.18微米,元件受到熱載子效應的影響而將會有新的物理現象產生。我們發現,元件最嚴重退化的程度不再是固定在量測Vd 值為0.1V而是Vd,p > 0.1V。且當元件操作在較高的溫度和外加基板偏壓時,此現象會更趨嚴重。在本篇論文中,我們將提出一個簡易的模型來解釋此現象。模型的理論簡述如下。隨著量測Vd值的增加,速度飽和區(velocity saturation region)所造成的遮蔽效應(saturation region effect)和較少的帶電介面陷阱(charged interface states)將減緩元件退化程度。然而汲極區(drain region)通道內載子的數量卻會隨著量測Vd值的增加而減少,導致退化程度更趨嚴重。所以Vd,p > 0.1V的現象便是由這兩種機制彼此間的相抗衡所造成的。
第三章是探討何種機制將會造成pMOSFET在較高閘極偏壓情況下加速退化的現象。經由實驗結果的驗證,我們發現,對PMOS元件而言,當元件偏壓在較高的閘極電壓時,超薄氧化層將導致閘極電子滲透到通道,與通道中的電洞產生復和(即所謂的歐傑復和效應),而電子電洞對復和所產生的能量,將導致更嚴重的熱載子效應。研究顯示,當元件操作在較高溫度及較低的偏壓情況時,此效應會更加嚴重。此外,F-N穿遂電流對高偏壓的閘極元件可靠度有一定程度的影響。研究發現,F-N穿遂電流對元件可靠度影響的嚴重程度受穿遂電流中電洞流成分多寡的影響。所以造成其對pMOSFET所造成的影響更勝於nMOSFET。
而在第四章中,我們將進一步的提出對本論文一些有待改進的地方。諸如:在第二章中可利用模擬軟體來增加模型準確度的方法和建議,或經由量測0.15μm製程技術元件,進一步確認模型的準確性。而對於第三章的部分,我們也將針對實驗上的缺點進行完整性的探討。
In this study, the effects of hot-carrier induced drain current degradation and gate leakage current induced by ultra-thin gate oxide on 0.18μm and 0.15μm CMOS devices will be investigated.
In the first chapter, the background of hot-carrier effects will be discussed. Results show that in deep submicron device, the worst case of hot-carrier induced drain current degradation is characterized at drain voltage higher than 0.1V which was well known as the worst case condition in long channel device. The worst case of characterized Vd was found to lager at higher temperature and substrate bias. A simplified model was presented to explain this new observation. Results show that the lowering of quasi-fermi level and the effect of the velocity saturation region (DL) contribute to the monotonically decrease ΔID/ID (%) as a function of measured VD. However, Qinv near the drain side also decreases since Vc increases. This mechanism results in the increase in DId/Id. Hence, the value of the worst case of characterized Vd is determined by this two competing mechanisms.
In the third chapter, enhanced hot-carrier induced Id degradation under high gate voltage stress was observed in pMOSFETs. Some mechanisms which may contribute to this phenomenon are discussed here。Results show that (I) F-N tunneling-current stress has finite effect on enhanced high gate voltage stress although gate oxide electric field as high as above 15MV/cm was applied. Anode hole injection model was adopted to explain the server F-N tunneling effect on pMOSFET than on nMOSFET. The hole component of the injected F-N tunneling-current was found to the dominant mechanism. (II) Electron tunneling from the gate due to ultra-thin gate oxide and Auger recombination assisted hot hole energy gain process were found to contribute to this phenomenon. Besides, this enhancement in Id degradation is more significant under high temperatures or lower supply voltages.
Finally, in the last chapter, future work is discussed.
Abstract (Chinese) I
Abstract (English) IV
Acknowledgements VI
Contents VIII
Figure Captions X
Lists of Tables XIV

Chapter 1 Introduction 1

Chapter 2 A New Observation in Hot Carrier Induced Drain Current Degradation in 0.18μm nMOSFETs

2.1 Introduction 5
2.2 Experiments 6
2.3 Results and Discussion 6
2.4 Conclusion 12

Chapter 3 Enhanced Hot-Carrier Induced Degradation in Ultra-Thin gate oxide pMOSFETs under high gate voltage stress

3.1 Introduction 13
3.2 Experiments 14
3.3 Results and Discussion 15
3.3.1 F-N stress effects induced by high gate voltage stress 18
3.3.2 Electron tunneling and Auger recombination enhance
hot-carrier effects 19
3.4 Conclusion 23

Chapter 4 Future Work 24

References 26
[1] Quader, K.N.; Ko, P.K.; Chenming Hu, “Projecting CMOS circuit hot-carrier reliability from DC device lifetime” IEDM, p. 511, 1993.
[2] C. Hu, s. c. Tam, F, C, Hsu, P. K. Ko, T. Y. Chan, and K. W. Terrill, “Hot-Carrier-Induced degradation –model, monitor, and improvement,” IEEE Trans. Electron Devices, vol.ED-23, p. 375, 1985.
[3] E. Takeda, Y. Ohji, and H. Hume, “High field effects in MOSFETs,” IEDM Tech. Dig., p. 60, 1985.
[4] F. C. Hsu, and S. Tam, “Relationship between MOSFET degradation and hot-electron induced interface-state generation,” IEEE Electron Device Lett., vol. EDL-5, p. 50, 1984.
[5] K. N. Quader, P. K. Ko, and C. Hu, “Simulation of CMOS circuit degradation due to hot-carrier effects,” in Proc. IRPS, p. 16, 1992.
[6] Doyle, B.; Bourcerie, M.; Marchetaux, J.-C.; Boudou, A., “Interface state creation and charge trapping in the medium-to-high gate voltage range (V/sub d//2or=V/sub d/) during hot-carrier stressing of n-MOS transistors” IEEE Trans. Electron Devices, vol. 37, p. 744, 1990.
[7] Shian Aur and Richard A. Chapman, “Gate Oxide Thickness Effect on Hot Carrier Reliability in 0.35μm NMOS Device” IRPS, p. 48, 1994.
[8] L. P. Chiang, C.W. Tsai, T. Wang, “Auger Recombination Enhanced Hot Carrier Degradation in nMOSFETs with Positive Substrate Bias: VLSI Tech., p. 132, 2000.
[9] E. Li, e. Rosenbaum, L. F. Register, J. Tao and P. Fang, “Hot Carrier Induced Degradation in Deep Submicron MOSFETs at 1000C” IRPS, p. 103, 2000.
[10] H. Hwang, Jung-Suk Goo, Hoyup Kwon, and Hyungsoon Shin, “Impact of Velocity Saturation Region on nMOSFET’s Hot Carrier Reliability at Elevated Temperatures” IRPS, p. 48, 1995.
[11] Rauch, S.E., III.; Guarin, F.J.; LaRosa, G., “Impact of E-E scattering to the hot carrier degradation of deep submicron NMOSFETs” EDL, p. 463, 1998.
[12] Wang-Ratkovic, J.; Lacoe, R.C.; MacWilliams, K.P.; Miryeong Song; Brown, S.; Yabiku, G., “New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures” IRPS, p. 312, 1997.
[13] E. Li, E. Rosenbaum, J. Tao, G. C-F Yeap, M-R. Lin, and P. Fang, “Hot Carrier Effects in nMOSFETs in 0.1μm CMOS Technology” IRPS, p. 253, 1999.
[14] Stewart E. Rauch III, Fernando J. Guarin, and Giuseppe LaRosa, “Impact of E-E Scattering to the Hot Carrier Degradation of Deep Submicron NMOSFET’s” EDL, p.463, 1998.
[15] Stewart E. Rauch III, Giuseppe La Rosa, Fernando J. Guarin, “Role of E-E scattering in the Enhancement of Channel Hot Carrier Degradation of Deep Sub-Micron NMOSFETs at high VGS Conditions” IRPS, p.399, 2001.
[16] N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “The impact bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scalling” Symp. On VLSI Technol., p.73, 1999.
[17] Lee, J.C.; Chen Ih-Chin; Hu Chenming, “Modeling and characterization of gate oxide reliability” IEEE Trans. Electron Devices, vol. 35, p. 2268, 1988.
[18] Schuegraf, K.F.; Chenming Hu, “Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation” IEEE Trans. Electron Devices, vol. 41, p. 761, 1994.
[19] M. F. Li, Y. D. He, S. G. Ma, B.-J. Cho, K. F. Lo, and M. Z. Xu, “Role of hole fluence in gate oxide breakdown,” IEEE Electron Device Lett., vol. 20, pp. 586-588, 1999.
[20] Y. Shi, T. P. Ma, S. Prasad, and S. Dhanda, “Polarity dependent gate tunneling currents in dual-gate CMOSFET’s,” IEEE Tran. Electron Devices, vol. 45, pp. 2355-2360, 1998.
[21] Markio Makabe, Taishi Kubota and Tomohisa Kitano “Bias-temperature degradation of pMOSFETs: mechanism and suppersion” IRPS, 2000, p. 205.
[22] Shirota, R.; Yamaguchi, T., “A new analytical model for low voltage hot electron taking Auger recombination as well as phonon scattering process into account” IEDM, p. 123, 1991.
[23] C. W. Tsai, S. H. Gu, L. P. Chiang, Tahui Wang, “Valence-Band Tunneling Enhanced Hot Carrier Degradation in Ultra-Thin Oxide nMOSFETs” IEDM, p. 139, 2000.
[24] A. Shanware, J. P. Shiely, and H. Z. Massoud, “Extraction of Gate Oxide Thickness of N- and P-Channel MOSFEETs Below 20A from the Substrate Current Resulting from Valence-Band Electron Tunneling” IEDM, p. 815, 1999.
[25] Kimizuka, N.; Yamamoto, T.; Mogami, T.; Yamaguchi, K.; Imai, K.; Horiuchi, T. “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling” Symp. On VLSI Technol., p. 73, 1999.
[26] Ken’ichi Uwasawa, Toyoji Yamaoto and Tohyu Mogami “A new Degradation Mode of Scaled p+ Polysilicon Gate pMOSFETs Induced by Bias Temperature (BT) Instability” IEDM, P.871, 1995
[27] Chenming Hu “VLSI ELECTRONICS: MICROSTRUCTURE SCIENC” VOL. 18 Chapter3 p.125~p.149
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 邱貴發(民87)。網路世界中的學習。理念與發展。教育研究資訊,6(1),20-27。
2. 林奇賢(民86)。全球資訊網輔助教學系統網際網路與國小教育。資訊與教育,58,2-11。
3. 吳美美(民85)。課程改革和資訊素養。社教雙月刊,74,32-39。
4. 吳美美(民85)。資訊時代人人需要資訊素養。社教雙月刊,73,4-5。
5. 吳明隆(民88)。新時代師生電腦素養的探究。教育部電子計算機中心簡訊,10,33-49。
6. 吳明隆(民87a)。電腦網路學習特性及其相關問題的省思。教育部電子計算機中心簡訊,9,23-39。
7. 吳明隆(民87)。教學科技與其教室生態典範的轉變。視聽教育雙月刊,40(1),11-20。
8. 徐新逸、楊昭儀(民88)。兒童自然科網路學習社群之設計與發展經驗。遠距教育,12,36-44。
9. 高鵬(民88)。公共圖書館新角色之研究--培育民眾網路素養之必要性。臺北市立圖書館館訊,16(3),52-66。
10. 張建原(民87)。電腦網路對教育的衝擊。教育部電子計算機中心簡訊。8701,28-31。
11. 黃久華(民89)。從國際終身學習思潮看網路學習市場之發展現況暨未來展望。臺北市立圖書館館訊,17(4),71-78。
12. 劉駿州(民85)。電腦網路的社區文化。社教雙月刊,74,16-19。
13. 盧信彰(民89)。「網路學習環境」建置之探討。生活科技教育,33(6),14-20。
14. 顏榮泉(民85)。全球資訊網在教學與學習上之應用探討。教學科技與媒體,25,33-41。