臺灣博碩士論文加值系統

因為液相沉積二氧化矽具有低花費以及在室溫成長的優點,所以我們採用此種方法成長在氮化鎵與氮化鋁鎵異質接面電晶體上.而實驗也證明了我們成功地使用液相沉積法來獲得一高崩潰電場與低漏電流的元件.
液相沉積二氧化矽法的沉積速率約每小時50nm的厚度.我們使用化學分析包括化學分析電子能譜儀和毆傑電子分析儀來分析我們所成長的物質為二氧化矽.而為了分析氧化層中的陷阱密度和特性,我們也用了電壓電流和電容電壓法來球出相關數值.其中,在氧化層厚度約為60nm時,我們得到陷阱密度約為5.9×1011cm-2eV-1,崩潰電場超過6MV/cm.在元件特性方面,我使用兩種結構.其中一種,中間沒有摻雜鎂的情形下,我們獲得轉導值約為80 mS/mm,而汲極最大電流約為70mA.而另外一種結構,我們在基板與導電層中加入一鎂的阻擋層後,獲得的轉導值約為40 mS/mm,而汲極最大電流為20 mA.同時他在Vgs為-4伏時,能夠將汲極電流完全關閉

The LPD have advantages of low cost and low temperature. And, the oxidation system is simply to operator. In this thesis, we successfully used liquid phase deposited (LPD) to grow silicon oxide layer on GaN/AlGaN device at low temperature (40℃). From that, we obtain a high breakdown electric field and low leakage current MOSHFETs.
The deposited rate of LPD is about 50nm/hr. We used chemical properties of Electron Spectroscopy of Chemical Analysis (ESCA) and Auger Electron spectroscopy (AES) to analyze the surface morphologies of oxide layer on GaN. Then, we used electrical properties of current-voltage and capacitance-voltage to analyze the quality of oxide layer on GaN. The interface trap density is about 5.9×1011 cm-2eV-1, breakdown field is over 6 MV/cm, and the leakage current density is about 10-7 A/cm2. The transconductance of GaN/AlGaN MOSHFET without Mg lightly doped layer is about 80mS/mm when Vgs=4V and Vds=15V, and the maximum Id current is 70mA. The transconductance of GaN/AlGaN MOSHFET with Mg lightly doped layer is about 40mS/mm when Vgs=-2V and Vds=10V. The maximum Id current is 20mA.And that, the cutoff voltage of MOSHFET with Mg lightly doped is –4V.

1 Introduction………………………………………1
1.1 Motivation…………………………………………1
1.2 Organization………………………………………3
2 The processes of liquid phase deposited SiO2…5
2.1 Introduction…………………………………………5
2.2 LPD systems and the speed of deposition……8
2.3 Chemical properties………………………………9
2.3.1 ESCA spectra……………………………………10
2.3.2 AES depth profile……………………………10
2.4 electrical properties…………………………11
2.4.1 current-voltage characteristics…………12
2.4.2 capacitance-voltage characreristics……12
2.5 Summary……………………………………………14
3 Fabrication processes of the GaN MOSHFET using LPD method………………………………………………16
3.1 Introduction………………………………………16
3.2 Device structure…………………………………17
3.2.1 The heterostructure without Mg buffer layer GaN MOSFET………………………………………17
3.2.2 The heterostucture with Mg buffer layer GaN MOSFET………………………………………………18
3.3 Fabrication processes…………………………18
3.4 Summary……………………………………………21
4 The DC characteristics of GaN MOSHFETs………22
4.1 Introduction………………………………………22
4.2 Characterization of GaN MOSHFETs……………23
4.2.1 The characterization of GaN MOSHFET without Mg buffer layer………………………………23
4.2.2 The characterization of GaN MOSHFET with Mg buffer layer…………………………………………24
4.3 Effect of device geometric size of gate length……………………………………………………25
4.4 Summary………………………………………………27
5 Conclusion……………………………………………28
5.1 Conclusions………………………………………28
5.2 Future works………………………………………28

[1]H. R. Wu, Y. W. Wang and M. P. Houng,” Liquid Phase Deposited SiO2 on GaN and Its Application to MOSFET”, Thesis for Master of Science, Department of Electrical Engineering, National Cheng Kung University, 2001
[2]H. Morkoc, S. Strite, G. B. Gao, M. E. Lin, B. Sverdlov and M. Burns, “Large-band gap SiC, Ⅲ-Ⅴ nitride, and Ⅱ-Ⅵ ZnSe-based semiconductor device technologies”, J. Appl. Phys., vol. 76, p.1363, (1994)
[3]S. J. Pearton, GaN AND RELATED MATERIALS, ch. 1. Gordon and Breach Science Publishers
[4]J. I. Pankove, E. A. Miller and J. E. Berkeyheiser, ”GaN electroluminescent diodes”, RCA Rev., vol. 32, p.383 (1971)
[5]H. P. Xin, R. J. Welty and C. W. cu, “GaN/sub 0.011/P/sub 0.989/-GaP double-heterostructure red light-emitting diodes directly grown on GaP substructures”, IEEE, Photon. Tech. Lett., vol. 12, iss. 8, p. 960, Aug, (2000)
[6]J. Edmond, H. kong and V. Dmitrieve, ”Blue/UV emitters from SiC and its alloys”, Inst. Phys. Conf. Ser. 137, p.515 (1994)
[7]S. J. Pearton, F. Ren, A. P. Zhang and K. P. Lee, ”Fabrication and performance of GaN electronic devices”, Materials Science and Engineering, R30 p.55, (2000)
[8]Y. Uzawa, Z. Wang, A. Osinsky and B. Komiyama, “Submillimeter wave responses in NbN/AlN/NbN tunnel junctions”,Appl. Phys. Lett. 66, p.1992, (1995)
[9]T. P. Chow, R. Tyagi, ”Wide bandgap compound semiconductors for superior high-voltage unipolar power devices”, IEEE Trans. Electron. Dev. 41, p.1481, (1994)
[10]M. A. Kahn, j. N. Kuznia, A. R. Bhattrai and D. T. Olson, “Metal conacts to gallium nitride”, Appl. Phys. Lett., vol. 62, p.2859, (1993)
[11]Z. Z. Bandic, P. M. Bridger, E.C. Piquette, T. C. McGill, R. P. Vaudo, V. M. Phanse and J. M. Redwing, “High voltage (450 V) GaN Schottky rectifiers,” Appl. Phys. Lett. Vol.74, p.1266, (1999).
[12]R. Gaska, J. W. Yang, A. Osinsky, Q. chen, M.A. Khan, A. O. Orlov, G. L. Snider and M. S. Shur, “Electron transport in AlGaN-GaN heterostructures grown on 6H-SiC substrates “, ,Appl. Phys. Lett. Vol. 72, p.707, (1998)
[13]Ren, F., Hong M., Chu, S.N.G., Marcus, M.A., Schurman, M.J., Baca, A., Pearton, S.J., and Abernathy, C.R., “Effect of temperature on Ga2O3(Gd2O3)/GaN metal-oxide-semiconductor field-effect transistors“, Appl. Phys. Lett., vol.73, p.3893, (1998)
[14]M. Hong, K. A. Anselm, J. Kwo, H. M. Ng, J. N. Baillargeon, A. R. Kortan., J. P. Mannaerts, A. Y. Cho, C. M. Lee,J. I. Chyi and T. S. Lay, “Properties of Ga2O3(Gd2O3)/GaN metal-insulator-semiconductor diodes”, J. Vac. Sci. Technol. B, 18(3), p.1453, (2000)
[15]H. C. Casey, G. G. Fountain, R. G. Alley, B. P. Keller, and S. P. DenBaars, ”Low interface trap density for remote plasma deposited SiO2 on GaN,” Appl. Phys. Lett. , vol. 68, p.1850, (1996)
[16]T. Homma, K. Katoh, Y. Yamada, and Y. Murao, ”A Selective SiO2 Film-Formation Technology Using LPD for Fully Planarized Multilevel interconnections”, J. Electrochem. Soc., vol. 140, No. 8, p.2410, (1993)
[17]W. J. Chang, M. P. Houng and Y. H. Wang, ”Investigation on the Conduction Mechanism of Ultrathin Fluorinated Silicon Dioxides”, Dissertation for Doctor of Philosophy, Department of Electrical Engineering, National Cheng Kung University, (2001)
[18]M. P. Houng, C. J. Huang, Y.H. Wang, N. F. Wang and W. J. Chang “Extremely low temperature formation of silicon dioxide on gallium arsenide”, J. Appl. Phys., vol.82, p.5788, (1997)
[19]M. P. Houng, Y. H. Wang, C. J. Huang, S. P. Huang, and J. H. Horng, “Quality optimization of liquid phase deposition SiO2 films on gallium arsenide”, Solid-State Electronics, vol.44, p.1917, (2000)
[20]W. S. Lu and J. G. Hwu, ” Reliable fluorinated thin gate oxides prepared by liquid phase deposition following rapid thermal process”, IEEE Electron Device Letters, Volume: 17 Issue: 4, P. 172, April, (1996)
[21]J. Y. Wu, Y. H. Wang and M. P. Houng, “Investigation and Application of Liquid Phase Chemical Enhanced Oxidation Technique on GaAs MOSFET’s”, Dissertation for Doctor of Philosophy, Department of Electrical Engineering, National Cheng Kung University, (2001)
[22]S. P. Murarka, “Thermal oxidation of GaAs”, Appl. Phys. Lett., Vol. 26, p. 180, (1975)
[23]D. N. Butcher and B. J. Sealy, “The thermal oxidation of GaAs”, J. Phys. D: Appl. Phys., vol. 11, p. 1451, (1978)
[24]G. Liu and X. Lin, “Scaling issues of LPD protocol”, Info-tech and Info-net, 2001. Proceedings. ICII 2001 - Beijing. 2001 International Conferences on, vol. 2, p. 110, (2001)
[25]J. L. Yeh and S. C. Lee, ” Amorphous-silicon thin-film transistor with liquid phase deposition of silicon dioxide gate insulator”, IEEE Electron Device Letters , vol. 20, iss. 3, p. 138, March, (1999)
[26]H. C. Casey, G. G. Fountain, R. G. Alley, B. P. Keller and S. P. Denbaars, “Low interface trap density for remote plasma deposited SiO2 on n-type GaN”, Appl. Phys. Lett., vol 68, iss. 13, p. 1850, March, (1996)
[27]E. H. Nicollian and J. R. Brews, MOS (Mteal Oxide Semiconductor) physics and technology, ch. 2,3,4. New Jersey: Artech House, 1982
[28]E. H. Nicollian and J. R. Brews, MOS (Mteal Oxide Semiconductor) physics and technology, ch. 8. New Jersey: Artech House, 1982
[29]M. A. Khan, X. Hu, G. Sumin, A. Lunev, J. Yang and M. S. Shur, “AlGaN/GaN Metal Oxide Semiconductor Heterostructure Field Effect Transistor”, IEEE Electron Device Letters, vol. 21, no. 2, p. 63, February, (2000)