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研究生:陳建豪
研究生(外文):Chien-Hao Chen
論文名稱:超薄氮化閘極介電層應用於深次微米互補式金氧半電晶體製程的研究
論文名稱(外文):The Study of Ultra-Thin Nitride-Related Gate Dielectrics for Deep Sub-Micron CMOS Process Application
指導教授:梁孟松陳世昌陳世昌引用關係方炎坤方炎坤引用關係
指導教授(外文):Mong-Song LiangShih-Chang ChenYean-Kuen Fang
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:202
中文關鍵詞:二氧化矽氮化矽遠端電漿氮化閘極介電層
外文關鍵詞:SiO2Si3N4remote plasmanitridationgate dielectric
相關次數:
  • 被引用被引用:2
  • 點閱點閱:453
  • 評分評分:
  • 下載下載:111
  • 收藏至我的研究室書目清單書目收藏:1
隨著CMOS技術的演進,閘極介電層厚度必須持續的縮減以得較高的電流驅動能力。然而,由於過高的閘極直接穿隧漏電流及硼摻質擴散等問題,傳統二氧化矽已不再適合當作閘極介電層的材料。因此,急需研發具較高介電常數及較佳硼擴散阻擋能力的新材料。在高介電質材料(High-K materials)成功導入量產之前,氮化氧化矽可說是最有希望成為下世代閘極介電層的材料。本論文的研究,係針對三種不同製程所研製的超薄氮化氧化矽材料的材料物性及其應用於CMOS元件的電特性作深入的探討及比較。
  首先,本論文回顧目前超薄二氧化矽特性的相關研究及其面臨縮減厚度時所產生的效應,包括:穿隧漏電流、硼摻質擴散、量子效應、複晶矽空乏效應等,及這些效應對元件操作、散熱、可靠度、厚度綷取的影嚮。另外,我們提出一種借由平帶電容值來綷取超薄氧化層厚度的方法,其可大為降低上述問題對厚度量測的侷限。
其次,我們研究以氨氣熱氮化法(NH3 thermal nitridation)所處理的超薄氮化氧化矽薄膜的特性。其中,物理特性包括熱氮化機制、氮分佈側圖、物性厚度的變化,及應用於CMOS元件的電特性包括能障高度、等效氧化層厚度、閘極漏電、載子移動率及其化重要元件參數等均有深入的研究。此外,這些特性在負型及正型CMOS元件上的差異也有詳細的探討與比較。研究結果顯示,此種氮化氧化矽除了衰退電洞移動率外,其於縮減厚度應用上具備絶佳的潛能。
  再則,我們對以遠端電漿氮化法(remote plasma nitridation)處理的超薄氮化氧化矽薄膜的物、電特性詳加研究。吾人發現,當基層二氧化矽厚於約2nm以上,此種氮化法可有效地降低等效氧化層厚度,精確控制氮分佈測圖且幾乎不會衰減載子移動率。然而,當基層二氧化矽薄於約2nm時,氮激子(nitrogen radicals)穿透的影嚮包括增加厚度,衰減電子移動率及可靠度等一一浮現。對於這些缺失,吾人深入研究,並提出“激子導致再氧化”及“電漿導致電子缺陷”機制模型來解釋。並在考量厚度、漏電流及移動率等諸因素下,對此種氮化法的厚度縮減極限作了預測。
  最後,吾人針對一種結合超薄氮化矽及二氧化矽的堆疊結構的閘極電介層來研究。研究重點在於底層材料及退火處理對此種結構的電特性的影嚮。結果發現,含氮的二氧化矽底層具較佳的元件效能。而氨氣退火及後續的一氧化二氮退火對此結構的漏電流、移動率及等效厚度等特性的影嚮上恰有相反的表現。因此可借由調整這二種退火處理,並針對應用的需求來進行元件特性的最佳化。
As the aggressive downscaling of CMOS technology continues, further reduction of gate oxide thickness is essential for low supply voltage and high driving capability. However, the excessive gate direct tunneling and the boron penetration issues phase out the use of conventional silicon dioxide gate dielectric as early as the 100nm CMOS process. The development of new gate materials with higher dielectric constant and better boron penetration immunity become necessary and urgent. Before the successful introduction of identified high-K materials, the nitride-related materials have been emerged as the most promising candidates for replacing silicon oxide as a gate dielectric for sub-100nm node. In this thesis, the major issues for the thickness reduction of silicon dioxide and the characteristics of ultra-thin nitride-related materials including NH3 thermal nitrided oxide, N2 remote plasma nitrided oxide, and nitride oxide stack are extensively investigated and discussed.

Firstly, we start with a review of the present understanding of general ultra-thin oxide issues, their mutual relationship, effects on the gate oxide integrity and consequences for oxide thickness scaling. Issues relating quantum mechanical tunneling current, boron penetration, polysilicon gate depletion, and its impacts on device operation, power consumption, reliability, and metrology for thickness measurement are comprehensively demonstrated. A novel and simple method to determine the ultrathin oxide thickness from measuring the flatband capacitance is presented as well.

Secondly, the characteristics and the feasibility of the ultra-thin (equivalent oxide thickness (EOT) =13~16Å) nitrided oxides formed by rapid thermal nitridation in NH3 ambient are thoroughly investigated. The physical properties including the nitridation mechanism, the nitrogen distribution profile and the physical thickness are studied. The electrical properties, which include barrier height lowering, effect, EOT, gate leakage reduction capability, carrier mobility, dielectric reliability, and other important device parameters are demonstrated. Their differences between N and PMOS are extremely studied as well. The results show this NH3 nitrided oxide exhibits excellent downscaling ability, except the undesirable hole mobility degradation.

Thirdly, we comprehensively investigate the physical and electrical characteristics of the ultrathin nitrided oxides formed by the advanced remote plasma nitridation approach. It was found that remote plasma nitrided oxide with base oxide thickness larger than ~20Å exhibits excellent nitrogen profile, good EOT and gate leakage reduction capability, and almost no degradation was observed in carrier mobility. However, the impacts of the nitrogen radicals penetration including thickness re-growth, additional electron mobility degradation, and plasma-induced damage were observed as base oxide thinner than ~20 Å. The radical-induced re-oxidation and plasma-induced electron trapping models are proposed to explain the above abnormal phenomena. Additionally, the downscaling limit of the remote plasma nitrided oxide is studied, based on the consideration of EOT, gate leakage criteria, and mobility degradation.

Finally, the electrical characteristics of the ultrathin nitride/oxide gate stack (~1.6nm) affected by the base oxide material and post deposition annealing are extensively studied. It was observed that the use of nitrogen-rich base oxide can effectively reduce the inconsistency at Si3N4/SiO2 interface and retard the nitrogen diffusion into substrate during post-deposition annealing, leading to a superior device performance. The opposite effects of the NH3 and subsequent N2O post annealing on the EOT, gate leakage reduction, and mobility of the ultra-thin nitride/oxide stack are also compared and discussed.
Contents
Abstract (Chinese) Ⅰ
Abstract (English) Ⅲ
Acknowledgment (Chinese) Ⅵ
Contents Ⅶ
Table Caption XI
Figure Captions XII

Chapter 1
Introduction
1.1 Overview of Challenges for Future Device Scaling…………………………. 1
1.2 Organization of the Thesis…………………………………………………… 4

Chapter 2
Major Issues for The Thickness Reduction of SiO2
2.1 Background and Motivation………………………………………………… 10
2.2 Gate Leakage Current……………………………………………………….. 11
2.2.1 Characteristics of Gate Direct Tunneling Current……………………… 11
2.2.2 Effects of Excessive Gate Direct Tunneling Current…………………... 14
2.3 Trade-Off between Boron Penetration and Polysilicon Depletion………….. 16
2.4 Determination of Ultrathin Oxide Thickness……………………………….. 17
2.5 Summary………………………………………………………………..…... 22

Chapter 3
Rapid-Thermal NH3 Nitrided Oxide
3.1 Background and Motivation………………………………………………… 42
3.2 Experimental………………………………………………………………… 45
3.3 Physical Properties Analysis………………………………………………… 46
3.3.1 Thermal Nitridation Mechanism………………………………………... 46
3.3.2 Nitrogen Distribution profile…………………………………………… 48
3.3.3 Physical Thickness Variation…………………………………………… 50
3.4 Electrical Properties Analysis……………………………………………….. 51
3.4.1 Reduction of Equivalent Oxide Thickness……………………………... 51
3.4.2 Flat-Band Voltage Shift………………………………………………… 54
3.4.3 Gate Leakage Current Characteristics………………………………….. 55
3.4.3.1 Barrier Height Lowering Effects………………………………... 56
3.4.3.2 Gate Leakage Reduction………………………………………... 59
3.4.4 Effective Mobility……………………………………………………… 61
3.4.5 Id-Vd Characteristics…………………………………………………… 63
3.4.6 Vt Roll-Off……………………………………………………………... 65
3.5 Dielectric Reliability………………………………………………………... 66
3.5.1 Charge Trapping………………………………………………………... 66
3.5.2 Charge to Breakdown………………………………………………….. 67
3.5.3 Time Dependent Dielectric Breakdown………………………………... 67
3.6 Summary……………………………………………………………………. 68

Chapter 4
Remote-Plasma N2 Nitrided Oxide
4.1 Background and Motivation……………………………………………….. 102
4.2 Experimental………………………………………………………………. 105
4.3 Nitrogen Distribution Profile………………………………………………. 106
4.4 Gate Leakage Current (Jg) and Equivalent Oxide Thickness (EOT)……… 108
4.4.1 Barrier Height Lowering Effect……………………………………….. 110
4.4.2 Jg and EOT Properties………………………………………………… 111
4.4.3 Impacts of Radical-Induced Re-Oxidation……………………………. 113
4.5 Effective Mobility…………………………………………………………. 117
4.5.1 Mobility Characteristics………………………………………………. 117
4.5.2 Impacts of Radical Penetration……………………………………….. 118
4.6 Nitridation Temperature Effect……………………………………………. 120
4.7 Boron Penetration Immunity ……………………………………………… 123
4.8 Reliability………………………………………………………………….. 124
4.8.1 Charge Trapping………………………………………………………. 125
4.8.2 Charge to Breakdown…………………………………………………. 126
4.8.3 Hot-Carrier Damage…………………………………………………... 126
4.9 Summary…………………………………………………………………... 127

Chapter 5
Nitride/Oxide Gate Stack
5.1 Background and Motivation………………………………………………. 166
5.2 Experimental……………………………………………………………… 169
5.3 Electrical and Physical Properties………………………………………… 170
5.3.1 Bottom Oxide Material Effects……………………………………….. 171
5.3.2 Two-Step Post-Deposition Annealing Effects………………………… 175
5.3.2.1 NH3 Annealing………………………………………………… 176
5.3.2.2 Subsequent N2O Annealing……………………………………. 178
5.4 Summary…………………………………………………………………... 179

Chapter 6
Conclusions and Prospects
6.1 Conclusions of This Study………………………………………………… 198
6.2 Suggestions for Future Work……………………………………………… 201

Appendix
Publication List……………………………………………………………………… i
Vita………...………………………………………………………………………..iii
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[5.1] The National Technology Roadmap for Semiconductors, Semiconductor Industry Association, San Jose, CA, 1997.
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