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研究生:吳志銘
研究生(外文):Chih-Ming Wu
論文名稱:應用場規劃邏輯陣列設計之動態電壓恢復器之研製
論文名稱(外文):A FPGA-Based Design of Dynamic Voltage Restorer
指導教授:黃世杰黃世杰引用關係
指導教授(外文):Shyh-Jier Huang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:105
中文關鍵詞:場規劃邏輯陣列電壓凹陷電壓驟降動態電壓恢復器
外文關鍵詞:sagnotchFPGADVR
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  • 被引用被引用:1
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本文提出一新型動態電壓恢復器,並予以應用於保護重要負載,以防止受到市電電壓干擾。傳統動態電壓恢復器對於電壓驟降具良好之補償效果,惟其響應速度過慢,因此無法有效解決如電壓凹陷等電壓暫態問題。對此,本文提出一新型架構,其有別於傳統動態電壓恢復器之輸出濾波器擺設方式,可快速地補償電壓以解決電壓暫態問題。本文控制器係採用類比與數位混合模式,利用場規劃邏輯陣列(Field Programmable Gate Array, FPGA)設計數位控制器,並藉由程式撰寫方式設計電路,以達到快速修改電路參數之優點。本文中實驗波形量測結果,並得知所提之架構確已具供電品質改善之效果,進而證實其可行性及實用價值。
In this paper, the novel deign of dynamic voltage restorer is proposed to protect important loads and restrict the unwanted disturbances. With this proposed circuit design, the drawbacks of traditional dynamic restorers such as slow response and poor voltage transients can be both effectively solved. By allocating the output filters in the appropriate places in the circuit, it is found not only the voltage sag problem can be compensated, but also the voltage transients can be resolved in an efficient manner. To facilitate the circuit design, the field programmable gate array (FPGA) is also employed for the digital controller design in the dynamic voltage restorer, thereby increasing the flexibility of circuit design while improving the dynamic performance significantly. This proposed circuit has been simulated in the laboratory, and experimented through the hardware validation. Test results confirm the feasibility of the deign approach for the applications considered.
中文摘要 I
英文摘要 II
誌謝 III
目錄 IV
表目錄 VII
圖目錄 VIII
符號說明 XII
第一章 緒論 1
1-1 研究背景與動機 1
1-2 目的及方法 3
1-3 內容大綱 3
第二章 動態電壓恢復器操作理論 5
2-1 簡介 5
2-2 系統架構及分析 5
2-3 輸出濾波器之設計方式 9
2-3-1換流器端濾波器型之動態電壓恢復器 9
2-3-2電力線端濾波器型之動態電壓恢復器 11
2-3-3本文所提系統之濾波器設計方式 11
2-4 控制系統設計 14
2-4-1 AC控制迴路 14
2-4-2 DC控制迴路 18
第三章 FPGA簡介 20
3-1 前言 20
3-2 FPGA之硬體架構 22
3-3 FPGA軟體設計 28
3-3-1 硬體描述語言 28
3-3-2 FPGA設計平台 31
第四章硬體架構 33
4-1 簡介 33
4-2 類比電路 33
4-2-1 交流電壓有效值運算電路 35
4-2-2 相位落後領先補償器 39
4-2-3 軟式啟動保護電路 41
4-3 數位電路 43
4-3-1 類比/數位轉換器控制電路 43
4-3-2 鎖相迴路 47
4-3-3 數位比例積分控制器 52
4-3-4 2’補數乘法器 55
4-3-5 脈波寬度調變器 57
4-4 主電力電路 60
4-4-1 換流器之控制架構 61
4-4-2 單相低通濾波器 63
4-4-3截止緩衝電路 64
4-4-4驅動電路 65
4-5 動態電壓恢復器之模擬結果 67
第五章 實驗結果 72
5-1 簡介 72
5-2 FPGA佈線圖與GATE使用率 73
5-3 市電發生電壓驟降測試 76
5-4 傳統架構與新架構之比較 87
5-5 市電電壓波形受諧波干擾之補償 92
第六章 結論與未來研究方向 94
6-1 結論 94
6-2 未來研究方向 94
參考文獻 96
附錄 101
作者簡介 104
著作權聲明 105
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