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研究生:陳家豪
研究生(外文):Ja-Hao Chen
論文名稱:二維解析閘極導致汲極漏電流模型與直流脈波熱載子效應在閘極導致汲極漏電流影響之研究
論文名稱(外文):Study of 2D Analysis Gate-Induced Drain Leakage (GIDL) Model and DC pulse Hot-Carrier Effect on GIDL of nMOSFETs
指導教授:王是琦王永和王永和引用關係
指導教授(外文):Shyh-Chyi WongYeong-Her Wang
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:124
中文關鍵詞:直接穿透漏電流
外文關鍵詞:gate-induced drain leakagedirect tunnelingleakage currentGIDL
相關次數:
  • 被引用被引用:0
  • 點閱點閱:347
  • 評分評分:
  • 下載下載:72
  • 收藏至我的研究室書目清單書目收藏:0
本論文中,我們對閘極導致汲極漏電流(GIDL)的模型,和直流脈波熱載子效應(DC pulse Hot-Carrier Effect)在汲極漏電流的模型做探討。首先,我們建立了用於金半氧場效電晶體(MOSFET)閘極導致汲極漏電流的三端可解析的直接穿透形式的穿透(band-to-band tunneling)電流模型。這個模型考慮了在閘極-汲極重疊區域的雜質參雜濃度、垂直電場、橫向電場、和因橫向電場所導致的電子橫向動量的增加,還有表面電位等參數。我們使用將電位近似常數的方法,將模型簡化成可析解的方程式,可將過去複雜的模型簡單化。這個模型所算的結果在廣偏壓與通道長度範圍之下均非常接近實際元件所量的結果。我們所建立的模型對於電機體的閘極導致汲極漏電流分析和電路模擬是非常有幫助的。
再者,由於閘極氧化層的退化會造成閘極導致汲極漏電流的退變,因此我們在此論文也討論氧化層可靠度的問題。我們把定電壓應力(constant-voltage stress)與定電流應力(constant-current stress)的變動和機制做了研究與比較。在實驗結果可以發現,應力電流的變化決定了氧化層的崩潰(breakdown)。對於定電壓應力,因為應力電流隨時間的增加而遞減,所以受陷電荷和介面能階密度隨著時間成T1/2βλ的關係。對於定電流,因為定電流造成受陷電荷產生速度固定,所以受陷電荷和介面能階密度隨著時間成線性的關係。我們也提出了定電壓的通過電流模型(passing current model)來解釋崩潰的機制,以及其與受限電荷分佈與受限電荷密度的相依性。
最後,我們對直流脈波熱載子效應(DC pulse hot-carrier effect)在高電廠下對閘極導致汲極漏電流影響做探討,並且研究應力造成的退化機制。我們改變了脈波的頻率、上升/下降時間以及振幅來做討論,並且對於在應力中熱電洞的注入、介面能階的產生以及熱電荷的注入對氧化層所破壞的貢獻做了驗證。我們從實驗發現在最大閘極電流應力(Ig,max stress)下,閘極導致汲極漏電流的退變會隨著派波的頻率與上升/下降時間的增加而增加,然而,在最大基極電流應力(Ib,max stress)下,漏電流的退變會隨著派波的頻率與上升/下降時間的遞減而增加。此結果對於直流脈波熱載子效應的分析是有幫助的。
The gate-induced drain leakage current model and the leakage degradation induced by DC pulse hot-carrier effect have been studied. First, an analytic three-terminal band-to-band tunneling current model for the gate-induced drain leakage current (GIDL) in an n-MOSFET is developed. This model considers impurity doping concentration, vertical field, lateral field and so-induced electron momentum enhancement, as well as the surface electrostatic potential in the gate-to-drain overlapped region. Based on a constant surface-potential approximation, a closed-form equation has been obtained instead of the complex integral-form in previous works. The results from this new model show good agreement with the measurement data over a wide range of gate and drain biases and device channel lengths. This work is useful for GIDL analysis in transistor design as well as in circuit simulation.


Moreover, because the gate-induced drain leakage current would be degradated after gate oxide aging, we also investigate the oxide realibility in this thesis. The evolution and model of breakdown mechanisms of constant-voltage and constant-current stress are investigated and compared. The results show that for both stressing methods, the transient evolution of stress current determines the breakdown. For constant-voltage stress, because the stress current decreases with time, the trapped charge and interface state density increases with stress time with a $T_{s}^{1/2 etalambda}$ dependence. For constant-current stress, due to the constant trapped charge generation rate, the trapped charge and interface state increases linearly with stress time. A passing current model for constant-voltage stress has been developed to explain the breakdown mechanism and its dependence on trapped charge distribution and trapped charge density.


Finally, we investigate that the DC Pulse hot-carrier stress effects on the degradation in gate-induced drain leakage in a high field regime and the mechanisms of stress-induced degradation are studied. In this work we investigate DC Pulse stress parameters in GIDL which include frequency, rise/fall time and amplitude of stressing pulse. The contribution of hot-hole injection, interface state generation and hot-electron injection in a period of transient stress are identified. It is found that the GIDL degradation increases with increased pulse frequency and rise/fall time under maximum gate current stress, while decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC Pulse hot-carrier stress reliability analysis under circuit operation.
Abstract i
List of Tables x
List of Figures xi
1 Introduction 1
1.1 Background 1
1.1.1 Physical Phenomena of GIDL 2
1.1.2 Mechanisms of GIDL 6
1.1.3 Models of GIDL 6
1.1.4 Hot-Carrier Effect 11
1.2 Organization 15

2 An Analytic Three-Terminal Band-to-Band Tunneling Model on GIDL 18
2.1 Introduction 18
2.2 Physical Phenomena of GIDL 19
2.3 Model 26
2.3.1 Three-Terminal Tunneling Current Model 26
2.3.2 Vertical Electrical Field 33
2.4 Experimental Results 36
2.5 The GIDL on 3.2nm of oxide thickness nMOSFETs 38
2.6 Conclusion 43

3 Breakdown and Stress-Induced Oxide Degradation Mechanisms 46
3.1 Introduction 46
3.2 Experiment 48
3.3 Constant-Voltage Breakdown Mechanism 52
3.3.1 Passing Current Model 52
3.3.2 Trapped Charge Distribution 64
3.4 Constant-Current Breakdown Mechanism 70
3.5 Stress-Induced Interface State Generation 72
3.6 Comparison of Positive and Negative Stresses 76
3.7 Conclusion 78
4 DC Pulse Hot-Carrier-Stress Effects on Gate-Induced Drain Leakage Current 83
4.1 Introduction 83
4.2 Experiment 86
4.3 Results and Discussion 90
4.3.1 DC Hot-Carrier Stress on nMOSFETs' 90
4.3.2 DC pulse Hot-Carrier Stress on nMOSFETs' 93
4.4 The failure criterion of GIDL 107
4.5 Conclusion 109
5 Conclusions 111
Reference 117
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