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研究生:喬駿
研究生(外文):Jiunn Chyau
論文名稱:薄膜液晶顯示器與直接記憶體存取控制器之智產設計及其在單晶片系統中之整合與驗證
論文名稱(外文):IP Design on TFT LCD and DMA Controllersfor SoC Integration and Verification
指導教授:劉濱達
指導教授(外文):Bin-Da Liu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:78
中文關鍵詞:單晶片系統智產薄膜液晶
外文關鍵詞:SoCIPTFT
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摘要
單晶片系統設計是目前積體電路設計的新趨勢,一個複雜的系統在單晶片系統設計中,可以快速的被設計完成以符合市場的需要,而這是基於一個可重複使用的智產模組資料庫,挑選需要的裝置並且加以整合來達成整個系統的需求。
在本篇論文中,我們依循了單晶片系統設計的原理,與智產設計的觀念,針對攜帶式應用產品,發展出一個單晶片系統平台,首先要以ARM公司的AMBA匯流排為藍本來建構出一個晶片上匯流排的標準介面與通用的包裝器,接下來設計薄膜液晶顯示器的控制器與直接記憶體存取控制器,此兩控制器都設計成可參數化以支援不同的控制裝置與傳輸模式,每個智產都經過功能與介面上的驗證,在必要的裝置都設計完畢後,我們將各個智產整合成一完整的系統,並配合適當的模型加以驗證,此一平台設計完成後,可以使用在其他特殊用途的智產設計,透過包裝器接上晶片上匯流排即可以進行驗證。
此單晶片系統平台實現在Xilinx VIRTEXE V2000EFG680 晶片上,最大時脈為24.764MHz,邏輯閘總數為129625。
ABSTRACT
System-on-a-chip (SoC) is a novel trend in IC design. A complex system can be designed efficiently for achieving the market requirement in SoC design. Moreover, SoC underlines the reuse of IP library, which can integrate a complete system according to the specification by appropriate device selection.
In this thesis, the principle of SoC design and the concept of IP design are conformed to develop a SoC platform for portable product application. Initially, the AMBA bus architecture of ARM corporation is referred to construct a on-chip-bus standard interface and generic wrapper. Then, the TFT LCD and DMA controllers are designed to be parameterizable for supporting different devices and transfer modes. Each IP has verified the function and interface. After completing the essential devices design, each IP is integrated into a complete system and verified with appropriate models. Furthermore, after the platform is fulfilled, it is used to design other specific IPs. These IPs can be connected to the on-chip-bus through the wrapper, and then verified. This SoC platform has been implemented on Xilinx VIRTEXE V2000EFG680. Maximum operating frequency is 24.764MHz, and the gate count for this design: is 129,625 in total.
CONTESTS
1. Introduction……………………………………………………………………1
1.1 Motivation……………………………………………………………………1
1.2 The profile of SoC system……………………………………………………2
1.3 Organization of the thesis………………………………………………………3
2. The Plan of SoC System Architecture and
the Concept of IP Design…………………………………………………4
2.1 The basic concept of SoC design………………………………………………4
2.1.1 Architecture of the SoC design………………………………………4
2.1.2 Design flow of SoC design……………………………………………5
2.1.3 The concept of on-chip-bus…………………………………………7
2.1.4 SoC design example…………………………………………………8
2.2 The plan and application of the SoC platform…………………………………9
2.3 The basic concept of reusable intelligent property design……………………11
2.3.1 Top-level IP design………………………………………………11
2.3.2 Subblock design……………………………………………………13
2.3.3 IP integration………………………………………………………15
3. The On-Chip-Bus and the Master Wrapper…………………………17
3.1 On-chip-bus system……………………………………………………………17
3.1.1 System feature……………………………………………………17
3.1.2 System description…………………………………………………18
3.1.3 Signal definitions on bus…………………………………………19
3.1.4 The bus operation and waveform…………………………………22
3.2 The concept of compatible interface wrapper…………………………………24
3.3 The generic master wrapper for on-chip-bus…………………………………25
3.3.1 The basic function of master wrapper………………………………25
3.3.2 Input/output ports definition…………………………………………26
3.3.3 Finite State Machine…………………………………………………28
4. The IP of LCD controller………………………………………………31
4.1 The introduction to LCD controller function…………………………………31
4.1.1 Feature………………………………………………………………32
4.1.2 Programmable parameter……………………………………………32
4.1.3 Supportable LCD panel types………………………………………33
4.2 The LCD controller architecture and each block function description………33
4.2.1 FIFO…………………………………………………………………33
4.2.2 Data Analyzer 8……………………………………………………34
4.2.3 Data Analyzer 16……………………………………………………34
4.2.4 Palette RAM…………………………………………………………36
4.2.5 Clock logic…………………………………………………………36
4.3 LCD Controller Register Definitions…………………………………………36
4.3.1 Control register 0……………………………………………………37
4.3.2 Control register 1……………………………………………………38
4.3.3 Control register 2……………………………………………………39
4.4 Interface Pins Description……………………………………………………41
4.5 The verification of LCD controller……………………………………………43
4.5.1 Integrator/AP overview……………………………………………43
4.5.2 ARM integration/CM7TDMI overview…………………………45
4.5.3 Logic module architecture…………………………………………46
4.5.4 Verification results…………………………………………………47
5.The IP of the DMA Controller……………………………………………50
5.1 The introduction of DMA controller function…………………………………50
5.1.1 Feature………………………………………………………………51
5.1.2 Programmable parameter……………………………………………52
5.2 DMA function description……………………………………………………52
5.2.1 Transfer Operation…………………………………………………52
5.2.2 Priority………………………………………………………………54
5.2.3 Reset…………………………………………………………………54
5.2.4 Interrupt……………………………………………………………55
5.2.5 Locked transfer……………………………………………………55
5.3 Register description…………………………………………………………55
5.3.1 Sou_Baddx…………………………………………………………55
5.3.2 Des_Baddx………………………………………………………57
5.3.3 Controlx……………………………………………………………57
5.3.4 Sou_Cadd…………………………………………………………58
5.3.5 Des_Cadd……………………………………………………………58
5.3.6 Config………………………………………………………………58
5.3.7 Current………………………………………………………………59
5.3.8 Control………………………………………………………………59
5.3.9 Temporary registers…………………………………………………60
5.4 Pin description…………………………………………………………………61
5.5 DMA verification and transfer waveform……………………………………63
5.5.1 DMA verification……………………………………………………63
5.5.2 DMA transfer waveform……………………………………………64
6. SoC System Integration and Verification………………………………66
6.1 SoC system integration………………………………………………………66
6.1.1 Designing and verifying the interfaces
between the IP and the other parts………………………66
6.1.2 Functional verification of the IP in the chip…………………………67
6.2 The verification of SoC system………………………………………………68
6.2.1 Interface verification………………………………………………69
6.2.2 Application verification……………………………………………70
6.3 System layout in FPGA………………………………………………………72
7. Conclusion and Future Work……………………………………………74
7.1 Conclusion……………………………………………………………………74
7.2 Future work……………………………………………………………………75
7.2.1 Physical design………………………………………………………75
7.2.2 Testing circuit………………………………………………………75
7.2.3 Software supported…………………………………………………75
7.2.4 Other peripheral devices……………………………………………76
References………………………………………………………………………77
[1] Product Information PrimeXsys Wireless Platform ARM Corporation,Cambridge, 2002.
[2] Rajsuman, Rochit and Artect House, System-on-a-Chip: Design and Test, Norwood, MA:Artech House, 2000.
[3] G. Budd and G. Milne, “ ARM7100-a high-integration, low-power microcontroller for PDA applications,” Compcon '96. 'Technologies for the Information Superhighway' Digest of Papers, 1996, pp. 182 –187.
[4] Z. Junchao; C. Weiliang and W. Shaojun “Parameterized IP core design,” in Proc. 4th Int. Conf. ASIC, 2001, pp.744-747.
[5] J. Biggs, N. Salter and A. Gibbons, ARM White Paper, Soft IP Deployment: Creating and Integration Complex Virtual Component, Synopsys Inc.
[6] M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, Boston, MA: Kluwer Academic, 1998.
[7] AMBA Specification (Rev 2.0) ARM Corporation, Cambridge, 1999.
[8] S. Furber, ARM System-On-Chip Architecture, Reading, MA: Addison-Wesley, 2000.
[9] R. Seepold and N. M. Madrid, Virtual Components Design and Reuse, Boston, MA: Kluwer Academic Publishers, 2001.
[10] S. Lee; S. Yoo and K. Choi, “Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model,” in Proc. 10th Int. Symp. Hardware/Softwarw Codesign, 2002, pp.199-204.
[11] PrimeCell Color LCD controller (PL110), ARM Corporation, Cambridge, 1999.
[12] StrongARM SA-1110 Microprocessor, Intel Corporation, 2000.
[13] TFT Color LCD Module M121-53DH Product Specifications, IMES Corporation, 2000.
[14] PrimeCell Single Master DMA Controller (PL081), ARM Corporation, Cambridge, 2001.
[15] M. M. Mano, Computer System Architecture, Eaglewood Cliffs, NJ: Prentice Hall, 1992.
[16] 8237A High Performance Programmable DMA Controller, INTEL Corporation, 1999.
[17] R. Usselmann, WISHBONE DMA/Bridge IP Core, Rev. 1.2, 2001.
[18] R.L. Lysecky, F. Vahid and T.D. Givargis, “Experiments with the peripheral virtual component interface,” in Proc. 13th Int. Symp. System Synthesis 2000, pp.221-224.
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