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研究生:陳冠霖
研究生(外文):Kuang-Lin Chen
論文名稱:異質性DSM系統上求效能峰值之自動重組機制
論文名稱(外文):Maximizing Speedup through Self-tuning of Node Allocation on Heterogeneous DSM Systems
指導教授:謝鍚堃
指導教授(外文):Ce-Kuen Shieh
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:55
中文關鍵詞:效能預測效能異質性分散式共享記憶體
外文關鍵詞:performance predictionDSMspeedupheterogeneous
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使用者利用平行處理系統的本意在於能夠提升程式的執行效能。一般而言,平行化程式在較大的系統尺寸比起較小的系統尺寸有明顯的效能提升。但在增加處理器數目之後,因平行處理而需維持記憶體一致性所引發的額外負擔,卻可能有增加的趨勢,而導致整體效能的下降。除此之外,今日在建構一平行處理系統時,常因中央處理器的進步,而使平行處理系統中各個節點的處理速度不一。倘若分散式共享記憶體系統能夠預測平行程式的執行時間,並且自動選擇一個最佳的系統組態使得此平行程式達到最佳的效能提升。如此一來,使用者就無須擔心究竟一開始所決定的系統尺寸是否最適合該平行程式,一切只要交給系統來決定就可以了。

在本論文,我們描述了Proteus上最佳化系統效能自動重組機制的設計與實現。Proteus系統是一個具有動態重組能力的分散式共享記憶體系統。我們為實現自動重組機制加上了能夠預測系統效能的方法。在觀察平行程式執行了數個回合之後,結合執行時的資訊去預測不同系統尺寸及不同節點處理器下的效能差異,並且依據差異選擇調整系統尺寸及相對應的處理器運算能力,以達成系統效能最佳化的目標。
Maximizing speedup for parallel applications is the major goal of the software distributed shared memory (DSM) systems. Parallel applications running in large system size can have better speedup than small system size. However, when we increase the number of nodes, the parallel overhead also increases because of maintaining the shared memory consistency. Besides, today it is common to construct a DSM system with different kinds of computing powers because of variety of speeds of CPU. If DSM systems can predict the execution time of applications and dynamically choose the best set of system configuration to maximize applications speedup, users don’t worry about the problem and can reduce execution time.
In this thesis, we describe the design and implementation of automatic reconfiguration for maximizing speedup in our system, Proteus, which supports the dynamic node reconfiguration. Our system collected runtime information, especially CPU power of nodes, and then predicted the speedup variance of different system sizes. From the predicted results, it would decide whether to reconfigure to the system size and select the best combination of processor powers to maximize speedup.
CONTENT……………………………………………………………………………I
TABLES……………………………………………………………………………...II
ILLUSTRATIONS…………………………………………………………………III
CHAPTER 1 INTRODUCTION……………………………………………………1
CHAPTER 2 RELATED WORK…………………………………………………...5
CHAPTER 3 DESSIGN ISSUES……………………………………………………8
3.1 Automatic Reconfiguration…………………………………………………..8
3.2 Prediction Model……………………………………………………………11
CHAPTER 4 IMPLEMENTAION………………………………………………...20
4.1 Proteus Architecture……………………………………………………….20
4.2 Reconfiguration Mechanism…..…………………………………………..24
CHAPTER 5 EXPERIMENTAL RESULTS………………………………….…..29
5.1 Experimental Environment and Applications……………………………29
5.2 Experimental Results and Analysis………………………………………30
5.2.1 Case I…………………………………………………………………………31
5.2.2 Case II……………………………………………………..…………37
5.2.3 Case III……………………………………………………………….45
5.2.4 Case IV……………………………………………………………….49
CHAPTER 6 CONCLUSION AND FUTURE WORK…………….…………….52
BIBLIOGRAPHY…………………………………………………………………..53
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