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研究生:顏呈機
研究生(外文):Cheng-Chi Yen
論文名稱:2.4GHzISM頻帶收發機射頻前端CMOSRFIC及使用二極體線性器CMOSPA之研製
論文名稱(外文):2.4GHz ISM-Band CMOS Transceiver RF Front-end and CMOS PA with Diode Linearizer
指導教授:莊惠如莊惠如引用關係
指導教授(外文):Huey-Ru Chuang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:81
中文關鍵詞:功率放大器收發機射頻線性器無線通訊
外文關鍵詞:Wireless CommunicationISM-bandTransceiverPALinearizerRFIC
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本論文以TSMC 0.25mm 1P5M CMOS製程研製2.4GHz ISM頻帶CMOS功率放大器以及單混頻器架構收發機之射頻前端CMOS RFIC。在CMOS功率放大器方面,在採用偏壓式二極體線性器架構之下,ACPR約有2.3dBc的提升(modulation: π/4 DQPSK, data rate: 48.6Kbps, channel spacing: 30kHz, channel BW: 24.3kHz),線性增益大於11.2dB,功率增加效率(PAE)大於28%,1dB增益壓縮點大於21.2dBm。而CMOS收發機射頻前端採取單混頻器架構,中頻為280MHz,包含低雜訊放大器(LNA)、收發開關(T/R switch)、被動開關型混頻器(passive switching mixer)、驅動功率放大器(driver PA)。
CMOS收發機射頻前端整合量測結果為: 在接收模式下,轉換增益為2dB(無中頻放大器),雜訊指數為6.2dB,input P1dB為-11dBm,在384kbps的π/4 DQPSK 調變訊號下,靈敏度為-101dBm(@BER=10-5),動態響應範圍為90dB。由於混頻器及T/R 收發開關的損耗過大,故串接兩個驅動功率放大器以提供發射模式足夠的增益; 在發射模式下,轉換增益為7.8dB,output P1dB為11.5dBm,在輸出功率為10dBm,而頻道間隔設為384kHz時,ACPR為-32dBc,EVM值為4.1%。
This thesis presents the development of 2.4GHz ISM-band transceiver front-end CMOS RFICs and a CMOS PA using diode linearizer fabricated in TSMC 0.25μm 1P5M CMOS process. The PA has linear power gain of 11.2dB, output P1dB of 21.2dBm and PAE of 28%. The PA uses an integrated diode connected NMOS transistor as the function of diode linearizer to improve linearity. Measurement results shows 2.3dB improvement in ACPR (modulation: π/4 DQPSK, data rate: 48.6Kbps, channel spacing: 30kHz, channel BW: 24.3kHz).
The 2.4GHz transceiver front-end CMOS RFICs includes LNA、T/R switch、passive switching mixer and driver PA and the IF frequency is at 280MHz. Measured results of the 2.4GHz transceiver front-end CMOS RFIC shows as follows (with 384kbps,π/4 DQPSK modulated signal). The receiving mode has 2dB conversion gain, 6.2dB noise figure, -11dBm IIP3, –101dBm sensitivity (@BER =10-5) and 90dB dynamic range. Due to the loss of mixer and T/R switch, we use two driver PA connected in series to acquire higher gain in transmitting mode. The transmitting mode has 7.8dB conversion gain, 11.5dB output P1dB, 4.1% EVM and -32dBc ACPR (channel spacing 384kHz).
第一章 緒論 1

第二章 CMOS RFIC設計概論

2.1 TSMC 0.25mm 1P5M CMOS製程元件簡介 5
2.1.1 元件模型與電路設計的關係 5
2.1.2 NMOS電晶體 5
2.1.3 MIM電容 6
2.1.4 電阻 7
2.1.5 螺旋式電感 8
2.1.6 bondwire及pad 9
2.2 CMOS功率放大器設計概論 10
2.2.1 功率放大器簡介 10
2.2.2 功率放大器架構介紹 12
2.2.3 功率放大器設計 15
2.3 CMOS低雜訊放大器設計概論 20
2.3.1 低雜訊放大器簡介 20
2.3.2 低雜訊放大器架構介紹 20
2.3.2 低雜訊放大器設計 23
2.3.2 低雜訊放大器增益控制的設計 25
2.4 CMOS混頻器設計概論 26
2.4.1 混頻器簡介 26
2.4.2 混頻器架構介紹 26
2.4.3 混頻器設計 28
2.5 CMOS收發切換開關設計概論 30
2.5.1 收發切換開關簡介 30
2.5.2 收發切換開關架構介紹 30
2.5.3 收發切換開關設計 32

第三章 使用二極體線性器之2.4GHz CMOS功率放大器

3.1 偏壓式二極體線性器操作原理 35
3.2 設計流程 37
3.3 模擬與量測 38
3.4 修正設計 45

第四章 2.4GHz 收發機射頻前端CMOS RFIC設計

4.1 2.4GHz單混頻器收發機射頻前端CMOS RFIC架構 47
4.2 2.4GHz CMOS低雜訊放大器設計與量測 48
4.2.1 低雜訊放大器架構 48
4.2.2 低雜訊放大器設計流程 48
4.2.3 低雜訊放大器模擬與量測 49
4.3 2.4GHz CMOS被動開關式混頻器設計與量測 53
4.3.1 被動開關式混頻器架構 53
4.3.2 被動開關式混頻器設計流程 53
4.3.3 被動開關式混頻器模擬與量測 54
4.4 2.4GHz CMOS收發切換開關設計與量測 57
4.4.1 收發切換開關架構 57
4.4.2 收發切換開關設計流程 57
4.4.3 收發切換開關模擬與量測 57
4.5 2.4GHz CMOS驅動功率放大器設計與量測 60
4.4.1 驅動功率放大器架構 60
4.4.2 驅動功率放大器設計流程 60
4.4.3 驅動功率放大器模擬與量測 61

第五章 2.4GHz 收發機射頻前端CMOS RFIC整合量測

5.1 2.4GHz單混頻器收發機射頻前端收發模式簡介 65
5.2 接收模式整合量測 66
5.3 發射模式整合量測 71
5.4 結果討論 76

第六章 結論 77

參考文獻 78
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