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研究生:楊智仁
研究生(外文):Chin-Jen Yang
論文名稱:以軟/硬體共同設計方式在SOC發展平台上實現JPEG多媒體系統
論文名稱(外文):Implementation of JPEG Multimedia System with Hardware/Software Co-design on SOC Development Platform
指導教授:劉濱達楊家輝楊家輝引用關係
指導教授(外文):Bin-Da LiuJar-Ferr Yang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:67
中文關鍵詞:系統單晶片軟/硬體共同設計影樣壓縮
外文關鍵詞:Software/Hardware Co-designJPEGSoC
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本研究利用軟/硬體共同設計及驗證方式在SOC發展平台(含有ARM7TDMI及其晶片組)上來實現JPEG多媒體系統。在經過了系統計算量的分析後,DCT與VLC均為重複性高的函數且佔整體的計算量約51%。因此我們決定將DCT與VLC的函數以硬體的方式實現。DCT則是採用遞迴架構實現,而VLC則是以管線化實現之。
在系統整合方面,運用一個Wrapper將所設計的晶片包裹起來作為與AHB匯流排溝通的介面。並以記憶體為基礎的介面作為晶片與ARM7 TDMI溝通的方式,因此在此設計中所設計的晶片扮演一被控者(slave)的角色,而ARM7 TDMI則是主控者負責複雜的控制與資料的存取。當程式執行到DCT或VLC時,由ARM7 TDMI將資料存到DCT或VLC模組裡,在固定週期後再由ARM7 TDMI將資料讀回以繼續程式的執行,反覆上述動作後,最後完成壓縮的程序。
在最後的驗證上,本系統已成功的壓縮大量的圖片資料,並可正確地由通用解壓縮程式解回。整合硬體在FPGA上的最高頻率可操作在22.364MHz,使用FPGA閘數為135K。
In this thesis, a JPEG multimedia system following the hardware/software co-design and co-verification principle is implemented on SOC development platform which includes ARM7TDMI microprocessor and chipset. From the analysis of computational JPEG system, DCT and VLC are highly repetitive and occupy 51% in the total computation. Therefore, we implemented DCT and VLC functions in hardware.The hardware of DCT is implemented in recursive architecture and VLC is in pipelined architecture.
Concerning the integration of JPEG system, we design a wrapper to serve as the communicational interface between the proposed chip and AHB bus. Then we apply RAM-based interface to communicate ARM7TDMI with the designed chip. Thus in this design, our chip plays a slave role, and ARM7TDMI plays a master role which is responsible for complex controls and data access. When JPEG programs run to DCT or
* The author ** The Advisors
VLC function, ARM7TDMI stores data into the local memory within designed chip. After a fixed numbers of cycles, ARM7TDMI reads out computed data from the chip and continue to execute the next functions in programs. ARM7TDMI will proceed the above actions until JPEG programs are finished.
In the final verification, the system has successfully compressed quite a few pictures, and these compressed pictures are able to be decompressed accurately and correctly by general JPEG decompression programs. The maximum frequency at which integrated hardware can be operated on FPGA is 22.364MHz, and the number of gate counts is 135K.
目 錄
1. 緒論......................................................................................................1

1.1 簡介..............................................................................................1
1.2 共同設計發展概況......................................................................2
1.3 相關工作......................................................................................3
1.4 本論文的組織..............................................................................4

2. JPEG壓縮暨SOC發展之方法.................................................5

2.1 離散餘弦轉換( Discrete Cosine Transform: DCT )...................6
2.2 量化(Quantization)..................................................................... 6
2.3 編碼模式.....................................................................................7
2.3.1 DC係數的編碼式.............................................................8
2.3.2 AC係數的編碼式.............................................................8
2.4 Huffman編碼程序......................................................................8
2.4.1 DC係數的Huffman編碼.................................................8
A. DC Huffman編碼表的架構...........................................8
B. DC係數的Huffman編碼過程......................................9
2.4.2 AC係數的Huffman編碼................................................10
A. AC Huffman編碼表的架構..........................................10
B. AC係數的Huffman編碼過程.....................................11
2.4.3 位元組填塞Byte stuffing................................................13
2.5 系統單晶片設計與發展台........................................................14
2.5.1 系統單晶片......................................................................14
2.5.2 系統單晶片之設計流程..................................................15
A. 傳統設計(Traditionaldesign)........................................16
B. 軟硬體共同設計 (Software/hardware co-design)........16
C. 系統單晶片設計 (SoC Design)...................................17
2.5.3 設計理念..........................................................................18

3. RDCT與VLC之硬體實現.......................................................21

3.1 JPEG計算量的程式分析..........................................................21
3.1.1 C程式計算量分析...........................................................21
3.1.2 ARM發展程式計算量分析............................................23
3.2 二維遞廻離散餘弦轉換之硬體實現........................................23
3.2.1 RDCT演算法描述...........................................................23
3.2.2 硬體設計..........................................................................28
3.3 VLC無失真壓縮之硬體實現...................................................29
3.3.1 硬體實現..........................................................................29
A. RLC單元設計...............................................................30
B. DPCM單元設計...........................................................31
C. 類別單元設計...............................................................32
D. Huffman查表單元........................................................33
E. 三級的資料包裝模組( Three stage data packer unit).....34
E.1第一級......................................................................34
E.2第二級......................................................................36
E.3第三級......................................................................36

4. JPEG壓縮系統在ARM發展平台的實現與驗證...............38

4.1 ARM系統發展平台介紹..........................................................38
4.1.1 ARM的發展系統(ARM Integrator/Ap)概要..................39
4.1.2 核心模組(Core module)...................................................41
4.1.3 邏輯模組(logic module)...................................................42
4.2 以記憶體為基礎的介面結合
(RAM-base Interface Connection).........................................43
4.3 JPEG硬體實現方法..................................................................45
4.4 時間分析....................................................................................46
4.5 壓縮比與PSNR.........................................................................46
4.6 FPGA合成與實現結果.............................................................50

5. 結論與未來工作.............................................................................52

5.1 結論............................................................................................52
5.2 未來工作....................................................................................53

附錄A. 基本的JPEG所應用到的編碼表.................................54
參考文獻.....................................................................................65






表 目 錄

表3.1 ARM發展程式的JPEG壓縮的計算量分析..............................23
表3.2 以位移累加方式近似餘弦值表..................................................29
表4.1 軟/硬體的比較.............................................................................46
表4.2 模擬結果......................................................................................47
表4.3 DCT於FPGA下載後資源使用情形與速度..............................50
表4.4 VLC於FPGA下載後資源使用情形與速度..............................51
表4.5 Total System於FPGA下載後資源使用情形與速度.................51
表A.1 亮度量化表..................................................................................54
表A.2 彩度量化表..................................................................................54
表A.3 亮度DC係數差值Huffman編碼表............................................55
表A.4 彩度DC係數差值Huffman編碼表............................................55
表A.5 亮度AC係數Huffman編碼表....................................................56
表A.6 彩度AC係數Huffman編碼表....................................................60
表A.7 DC係數的類別表........................................................................64
表A.8 AC係數的類別表........................................................................64









圖 目 錄

圖2.1 JPEG基本的系統方塊圖.............................................................5
圖2.2 Zig-Zag掃描順序.........................................................................7
圖2.3 DC係數的差值編碼過程............................................................10
圖2.4 AC係數的Huffman編碼程序...................................................12
圖2.5 對於非零AC係數的編碼程序..................................................13
圖2.6 單晶片系統的普遍架構..............................................................15
圖2.7 傳統設計流程..............................................................................16
圖2.8 軟硬體共同設計流程..................................................................17
圖2.9 系統單晶片設計流程..................................................................18
圖2.10 軟/硬體共同設計及驗證.............................................................19
圖3.1 JPEG壓縮的流程圖....................................................................22
圖3.2 JPEG計算複雜度分析................................................................22
圖3.3 偶數部分的DCT係數之遞回架構............................................26
圖3.4 奇數部分的DCT係數之遞回架構............................................27
圖3.5 二維遞回離散餘弦轉換..............................................................28
圖3.6 JPEG無失真壓縮系統硬體設計方塊流程圖............................30
圖3.7 RLC單元的示意圖.....................................................................31
圖3.8 DPCM模組設計圖......................................................................32
圖3.9 類別單元演算過程......................................................................33
圖3.10 Huffman編碼對照單元...............................................................34
圖3.11 排列第一級方塊圖......................................................................35
圖3.12 排列第一級演算過程..................................................................35
圖3.13 排列第二級的方塊圖..................................................................36
圖4.1 ARM發展板之系統....................................................................39
圖4.2 系統整合平台的系統方塊圖......................................................40
圖4.3 核心模組的架構..........................................................................41
圖4.4 邏輯模組的架構..........................................................................42
圖4.5 界面整合示意圖..........................................................................44
圖4.6 系統整合發展板上的記憶體空間位址分配圖..........................44
圖4.7 硬體實現方法..............................................................................45
圖4.8 在表4.2中color1的測試樣本.......................................................48
圖4.8 在表4.2中color2的測試樣本.......................................................49
參考文獻
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9. D. A. Luthi, T. Po, P. A. Ruetz, “A video-rate Jpeg chip set,” in Proc. IEEE Cust. Int. Circuits Conf., pp. 26.2.1 -26.6.4, 1992.
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13.J. L. Wang, C. B. Wu, B. D. Liu, J. F. Yang, “Implementation of the discrete cosine transform and its reverse by recursive structures,” in Proc. IEEE Workshop on Signal Processing Systems, 1999, pp.120-130.
14.ITU/CCITT, Recommendation T.81, Digital compression and coding of continuous-tone still images, Sep. 1992.
15.J. L. Mitchell, W. B. Pennebaker, C. E. Fogg, and D. J. LeGall, MPEG Video Compression Standard, New York, Chapman & Hall, 1996.
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22.M. Barbero, Succhi, and H. Bailon, “A flexible architecture for a HDTV codec based on DCT,” Signal Process. of HDTV II, pp. 587-594, L. Chiariglione, Ed. Elsevier, 1990.
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