臺灣博碩士論文加值系統

摘要
MP3 音樂壓縮格式為MPEG 所制定的數位音響壓縮標準，其優越性已被廣泛地應用於網路傳輸及無線多媒體系統之播放與儲存。其中以逆改良型離散餘弦轉換(IMDCT)與合成濾波器組(Synthesis Filter Bank)是MP3 解碼流程中時間複雜度高且計算方式固定的兩個步驟。
在本論文中，我們將逆改良型離散餘弦轉換和合成濾波器組中的矩陣化轉換(Matrixing)皆設計成遞迴式硬體架，並以軟/硬體共同設計的方式將MP3 播放系統驗証於SoC 發展平台上。除此之外，硬體與發展平台之間的設計方式是採用可擴充式架構，可以任意增添或更改系統模式。
遞迴式逆改良型離散餘弦轉換與矩陣化轉換的硬體設計是使用Verilog HDL 撰寫，採用Xilinx Foundation 4 軟體模擬與合成，燒錄於發展平台上的FPGA，最後再搭配ARM 處理器以達成MP3 播放系統。其硬體架構的合成結果為103k 邏輯閘，時脈速度為14.3MHz。

MP3, the well-known abbreviation of MPEG-1 audio Layer 3 is categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression. For its versatile superiority, MP3 has been widely used in Internet transmission and wireless multimedia communication or storage applications. The inverse modified discrete cosine transform (IMDCT) and synthesis filter bank are the two critical procedures with high time complexity but regular computation. In this thesis, we propose the recursive hardware structures for IMDCT and matrixing transform of synthesis filter bank. Furthermore, MP3 player system following Hardware/Software co-design methodology is developed and verified on SoC development platform. Besides, the design of interface between hardware and development platform is expandable. System mode can be added or changed.
The hardware design of recursive inverse modified discrete cosine transform and matrixing is coded by Verilog HDL and then simulated and synthesized with Xilinx Foundation 4. The synthesized circuit is downloaded into FPGA on the development platform and cooperates with ARM processor to complete the MP3 system. The synthesis results show that gate count is 103k gates and clock rate is 14.3 MHz.

1. 緒論………….…………………………………………………… 1
1.1 研究動機………………………………………………………. 1
1.2 各章節摘要……………………………………….…………… 2
2. MPEG音訊壓縮標準總覽………………….………………… 4
2.1 ISO/MEPG 音訊壓縮標準………………….………….……… 4
2.2 MPEG-1 音訊壓縮標準………...……………………………… 6
2.2.1 MPEG-1 Layer 3 編碼標準…………….………….……… 6
2.2.2 MPEG-1 Layer 3 解碼標準…………….………….……… 10
2.3 MPEG-2 音訊壓縮標準………………….………….…………. 13
2.4 MPEG-4 音訊壓縮標準………...……………………………… 15
3. 系統單晶片設計與發展平台…………….…………………... 16
3.1 系統單晶片………………….………….……………………... 16
3.2 系統單晶片之設計流程……...……………………………….. 18
3.2.1 傳統設計…………….………….………………………… 18
3.2.2 軟/硬體共同設計…………….………….………………... 19
3.2.3 系統單晶片設計…………….………….……………….... 20
3.3 SoC 發展平台………………….………….…………………... 21
3.3.1 SoC 發展平台的功能…………….………….…………… 21
3.3.2 SoC 發展平台的設計流程…………….………….……… 22
3.4 以記憶體為基礎的介面整合………...……………………….. 23
4. 利用遞迴式架構建立MP3播放系統…………….………… 26
4.1 逆改良型離散餘弦轉換的遞迴式架構………………………. 26
4.2 合成濾波器組的遞迴式架構…………………………………. 31
4.3 重疊動作與資料儲存的方式…………………………………. 35
5. 在SoC 發展平台上實現MP3 播放系統…………………. 37
5.1 硬體實現………………………………………………………. 37
5.1.1 遞迴式核心之設計……………………………………….. 38
5.1.2 逆改良型離散餘弦轉換的前處理與後處理設計……….. 40
5.1.3 重疊相加………………………………………………….. 41
5.1.4 矩陣化的前處理與後處理設計………………………….. 43
5.2 記憶體之安排…………………………………………………. 45
5.3 即時播放之可能性……………………………………………. 46
5.4 搭配SoC 發展平台以實現MP3 播放系統………………….. 47
5.5 硬體效能………………………………………………………. 48
6. 結論………………………………………………………………. 51
6.1 總結……………………………………………………………. 51
6.2 未來方向………………………………………………………. 52

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