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研究生:黃永霖
研究生(外文):Yong-Lin Huang
論文名稱:具改良偏移誤差平均化技術的折疊與內插式類比/數位轉換器
論文名稱(外文):A High-speed Folding and Interpolating A/D Converter With Improved Offset Averaging Techniques
指導教授:郭泰豪
指導教授(外文):Tai-Haur Kuo
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:91
中文關鍵詞:偏移誤差平均化技術折疊
外文關鍵詞:averaging techniquefoldingoffset
相關次數:
  • 被引用被引用:4
  • 點閱點閱:252
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  • 下載下載:71
  • 收藏至我的研究室書目清單書目收藏:0
高位元速度的資料傳送應用如DVD 播放器和Gigabit 以太網路
不斷地需求更高速的類比/數位轉換器。在高速操作下,時脈誤差和
失真現象會限制轉換器的效能。為了達到高速操作而不至惡化失真問
題,一般會比較傾向於使用開回路平行式架構的類比/數位轉換器。
其中,採用折疊與內插式架構的類比/數位轉換器可放鬆其在速度、
準確度與功率消耗上的取捨。
本篇論文即詳細討論一個高速、中等解析度之折疊與內插式類比
/數位轉換器的設計,其涵蓋了三種主要功能,分別是放大、類比前
端處理與比較。為了降低折疊信號達到穩態值所需的時間,因此加入
了短路用開關及一些電路技巧。為了降低偏移誤差進而提高比較的準
確度,本論文提出兩種改良式的平均化技術,經由詳細的分析後可證
明這些技術比之前的方法更能有效地降低偏移誤差。佈局後的模擬結
果證實此類比/數位轉換器可操作在400MS/s ,以及在2.5 伏特的電壓
供應下消耗405mW 的功率。當輸入信號為50MHz 時,可以達到6.1
位元的有效解析度。整個類比/數位轉換器的晶片面積為
1.3x1.6mm
2 ,採用TSMC 0.25um ,1P5M 的CMOS 混和信號製程。
The high-bit-rate data communications such as DVD playback and Gigabit Eth-
ernet are spurring on the conversion rate of A/D converters. With the increasing
conversion rate, the main problems that impair the performance are the timing in-
accuracies and distortions. To provide a fastest path to quantize an analog signal
without aggravating the distortion problems, the parallel A/D architectures by using
only open-loop analog signal processing are preferred. Among them, the folding and
interpolating A/D converter can relax the trade-offs among the speed, accuracy, and
power dissipation.
This thesis examines the design of high-speed, medium-resolution(8 bits) folding
and interpolating A/D converters in terms of three basic functions, namely, amplifica-
tion, analog preprocessing, and comparison. To reduce the settling time for processing
the folded analog signal, shorting switches and some circuit techniques are added. To
perform a precise comparison with less offset, two proposed averaging techniques are
analyzed and proven to be more efficient than the previous implementation. The
post-layout simulation demonstrates the experimental 8-bit A/D converter can clock
at 400MSample/s with a power dissipation of 405mW from a 2.5 V supply voltage.
With a input frequency of 50MHz, 6.1 effective bits are obtained. The chip area is
1.3x1.6mm2 in TSMC 0.25um CMOS 1P5M mixed-signal process.
Abstract
Contents
1 Introduction.................................1
1.1 Motivation.................................1
1.2 Applications...............................2
1.3 Thesis Organization........................3

2 Review of High-speed CMOS ADC Architectures..5
2.1 Full flash ADC.............................5
2.2 Pipelined or Multistage ADC................6
2.3 Time-interleaved ADC.......................7
2.4 Folding ADC................................8

3 Design Techniques of A Folding ADC...........11
3.1 Averaging and Interpolating Technique......12
3.1.1 One-stage averaging......................12
3.1.2 Interpolating............................26
3.1.3 Averaging placement......................31
3.2 Dynamic Performance Enhancement............35
3.2.1 Adding front-end track-and-hold circuit..35
3.2.2 Comparison among different track-and-hold topologies.....................................39
3.3 Special Techniques and Design Issues.......42
3.3.1 Offset storage...........................42
3.3.2 Cascaded folding and interpolating.......45
3.3.3 Timing accuracy..........................47
3.4 Architectural Design of A High-speed 8-bit FAI ADC........................................49

4 Circuit Implementation: An 8-bit 400MS/s ADC.55
4.1 Front-end Track-and-hold Circuit...........55
4.2 Adding Preamplifiers.......................58
4.3 Folder and Interpolator....................61
4.4 Comparator and Error Correction............65
4.4.1 High-speed comparator design issues......65
4.4.2 Error correction.........................68
4.5 Bit-synchronization and Other Digital Circuits
...............................................69
4.5.1 Bit-synchronization principle............69
4.5.2 Miscellaneous Circuits...................70
4.6 Whole Chip Considerations..................72
4.6.1 Supply and ground bounce.................72
4.6.2 Input matching and clock generation......75

5 Simulation and Measurement Results...........78
5.1 Layout and Simulation Results..............78
5.2 PCB Design and Measurement.................83

6 Conclusion...................................86
Reference......................................88
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