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研究生:洪忻煒
研究生(外文):Shin-Wei Hung
論文名稱:考量多重設計參數限制之單晶片系統測試排程
論文名稱(外文):Test Scheduling for Core-Based SOC Design Under Multiple Constraints
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
畢業學年度:90
語文別:英文
論文頁數:46
中文關鍵詞:單晶片系統測試測試測試排程
外文關鍵詞:test schedulingtestingSOC testing
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在以核心電路(Core)為基礎的單晶片系統上,可能包含了數十個或上百個核心電路,如何在符合諸多設計參數的限制下,以最短的時間完成所有核心電路的測試,是個很大的挑戰。本論文中,我們提出一個測試排程的解決方案,其目的是在符合所有設計參數限制下,有效率地決定所有測試集的時間順序,使得總測試時間為最小。
我們考量的設計參數包括功率消耗、測試存取機制之寬度(TAM Width)、資源共享(Resource Sharing)、測試優先權(Precedence)以及多重測試集。我們也提出一個雙重二維裝箱模型(Dual Rectangle Bin-Packing Model)以及最佳位置(Best-Fit)演算法來解決這個問題。
以下茲列舉本測試排程方案的特點:
1. 第一個同時考量多重設計參數限制的測試排程方案。
2. 可同時考量上千個核心電路。
3. 可在數秒鐘之內得到排程結果。
4. 在短時間內考量上千個核心電路,仍然可得到很好的排程效率。
5. 與相關論文比較,在只有數十個核心電路以及考量較少的設計參數限制情況下,仍能得到不錯的結果。
A test scheduling methodology for core-based SOC design is developed. The main objective of this methodology is to efficiently identify a test schedule that requires minimum test time under various constraints. These constraints include maximum power consumption, limited test access mechanism (TAM) width, resources shared by different cores, test precedence between test sets, and multiple test sets required by a single core. The efficiency of our method is due to a proposed dual rectangle bin-packing model and an efficient algorithm based on this model.
The distinguishing features of our approach are listed below:
l. It is the first one to consider multi factors including power consumption, TAM width, resource sharing, precedence and multiple test sets concurrently.
2. The approach can deal with thousands of test sets simultaneously.
3. The proposed algorithm can obtain the results in seconds for an SOC with thousands of cores.
4. Though the program considers multiple constraints and a large number of test sets, its scheduling efficiency is still quite good.
5. Though aiming at handling thousands of cores, while considering tens of cores with less constraints, we can get a comparable scheduling results with previous work in a much shorter time.
CHAPTER 1 INTRODUCTION 1
1.1 THE IMPORTANCE OF TEST SCHEDULING 1
1.2 FEATURES OF PROPOSED SCHEDULING METHODOLOGY 2
1.3 ORGANIZATION OF THESIS 3
CHAPTER 2 PREVIOUS WORK 4
2.1 GRAPH BASED MODEL SCHEDULING 5
2.2 ILP BASED MODEL SCHEDULING 7
2.3 BIN-PACKING BASED MODEL SCHEDULING 8
CHAPTER 3 TEST SCHEDULING 10
3.1 TEST CONSTRAINT DEFINITION 10
3.1.1 TAM Width 11
3.1.2 Power Dissipation 12
3.1.3 Resource Sharing 14
3.1.4 Precedence 15
3.1.5 Multiple Test Sets 15
3.2 DUAL RECTANGLE BIN PACKING MODEL 16
3.2.1 One-dimensional Bin Packing 16
3.2.2 Two-dimensional Bin Packing 18
3.2.3 Dual Rectangle Bin Packing Model 19
3.3 TEST SCHEDULING ALGORITHM 21
3.3.1 The Scheduling Methodology 21
3.3.2 Multi_Factor_Scheduler Algorithm 23
3.3.3 Input / Output Files 29
CHAPTER 4 EXPERIMENTAL RESULTS 32
4.1 PLATFORM AND PROGRAMMING LANGUAGE 32
4.2 PARAMETERS OF TESTBENCH 32
4.3 EXPERIMENTS WITH 5 CONSTRAINTS 34
4.4 EXPERIMENTS WITH OPTIMAL TESTBENCH 38
4.5 COMPARISONS WITH OTHER WORK 41
CHAPTER 5 CONCLUSIONS 42
REFERENCES 43
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