跳到主要內容

臺灣博碩士論文加值系統

(54.91.62.236) 您好!臺灣時間:2022/01/18 00:12
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:曾瑞鉉
研究生(外文):Ruei-Shiuan Tzeng
論文名稱:運用三角調變器之內建式自我測試電路於類比數位轉換器
論文名稱(外文):A Sigma-Delta Modulation Based BIST for A/D Converter
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:77
中文關鍵詞:類比數位轉換器之內建式自我測試類比電路測試測試類比數位轉換器內建式自我測試
外文關鍵詞:testingBISTADC BISTADCanalog circuit testing
相關次數:
  • 被引用被引用:1
  • 點閱點閱:326
  • 評分評分:
  • 下載下載:84
  • 收藏至我的研究室書目清單書目收藏:1
本論文中提出了兩個內建式自我測試策略,應用於量測類比數位轉換器之四個主要測試參數,即偏移誤差(Offset Error)、倍率誤差(Gain Error)、整體非線性誤差(Integral Nonlinearity Error)及差分非線性誤差(Differential Nonlinearity Error)。第一個測試策略可應用於測試單晶片系統內部的類比數位轉換器。以三角調變器為基礎設計一個內建式弦波信號產生器,以產生類比和數位弦波信號,藉由此類比和數位弦波信號,由弦波統計方式以近似方程式求得待測參數。此一架構具有下列優點:1) 可量測各頻率之參數; 2) 測試精準度高; 3) 可作動態弦波測試; 4) 晶片面積需求小。第二個測試策略應用於獨立之類比數位轉換器。利用類比濾波器之相位差和統計各量測的數位碼是否介於容許範圍內,判斷待測電路參數是否正確。此一架構具有下列優點:1) 可量測各頻率之參數; 2) 測試精準度高; 3) 可利用動態弦波進行測試; 4) 架構易於設計與實現。
我們以八位元類比數位轉換器為例,在TSMC 0.35μm 1P4M製程下針對上述兩項測試策略架構進行設計,經由Verilog-XL、Matlab與Simulink軟體模擬及驗証可以得知本論文所提出的測試策略其精確度可達到0.05 LSB。
In this thesis, two built-in self test (BIST) methodologies have been developed to measure the four parameters of the A/D converters: offset error, gain error, integral nonlinearity error, and differential nonlinearity error. The first methodology can be used to test the A/D converter in a system-on-a-chip (SOC). A sigma-delta modulation based signal generator is designed to concurrently produce analog and digital sinusoidal signals on chip. By the sinusoidal histogram technique, the parameters can be extracted by the approximated equations. This structure has the following advantages: 1) parameter measurement capability for different frequencies; 2) high accuracy; 3) dynamic sinusoidal testing capability; 4) low chip area overhead. The second methodology is used to test the stand-alone A/D converters. By utilizing the phase delay of the analog filter and statistic measured codes, whether the device under test is correct or not can be determined. This structure has the following advantages: 1) parameter measurement capability for different frequencies; 2) high accuracy; 3) dynamic sinusoidal testing capability; 4) easy to design and implement.
The proposed structures are designed and simulated in an 8-bit A/D converter by using the TSMC 0.35μm 1P4M technology. With the Verilog-XL, Matlab, and Simulink tools, it is shown that the accuracy of offset error test, gain error test, integral nonlinearity error test, and differential nonlinearity error test are all less than 0.05 LSB.
Contents
1 Introduction 1
1.1 Motivation 1
1.2 Organization of Thesis 3
2 Background and Previous Work 5
2.1 Background 5
2.1.1 Basic Characteristics of A/D Converters 5
2.1.1.1 Parameters VOSE, GFSE, DNL, and INL 6
2.1.1.2 Other Performance Metrics 8
2.1.2 Analog Sinusoidal Signal Generator 9
2.1.2.1 Digital Resonator Circuit 10
2.1.2.2 First-Order ΣΔ Modulation Based Signal Generator 15
2.1.2.3 Second-Order ΣΔ Modulation Based Signal Generator 20
2.2 Previous Work 23
2.2.1 Space Domain Testing 23
2.2.2 Frequency Domain Testing 26
3 Methodology Ⅰ: BIST for A/D Converters in SOC 27
3.1 Architecture for Sinusoidal Histogram BIST 27
3.2 Digital Sinusoidal Reference Signal 28
3.2.1 First-order ΣΔ Modulation Based Reference Signal Generator 28
3.2.2 Second-order ΣΔ Modulation Based Reference Signal Generator 35
3.2.3 Comparison 39
3.3 Experimental Results 40
3.4 Summary 46
4 Methodology Ⅱ: BIST for Stand-Alone A/D Converters 47
4.1 Architecture for Stand-Alone A/D Converters 47
4.2 Error Band Method 48
4.2.1 Error Band Theory 49
4.2.2 Experimental Results 54
4.3 Analog Filter 61
4.4 Time Decomposition Method 66
4.4.1 Time Decomposition Theory 66
4.4.2 Experimental Results 68
4.5 Summary 71
5 Conclusions and Future Work 72
5.1 Conclusions 72
5.2 Future Work 73
[1].I. H. S. Hassan, K. Arabi, and B. Kaminska, “Testing Digital to Analog Converters Based on Oscillation-Test Strategy Using Sigma-delta Modulation,” Proc. of International Conference on VLSI in Computers and Processors, pp. 348-352, 1998.
[2].G. W. Roberts, “Metrics, Techniques and Recent Developments in Mixed-Signal Testing,” Proc. of International Conference Computer Aided Design, pp. 514–521, 1996.
[3].M. Burns, and G. W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, Inc., 2001.
[4].D. Johns and K. Martin, Analog Integrated Circuit Design, New York: John Wily & Sons, Inc., 1996.
[5].G. W. Roberts, A. K. Lu, Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, 1995.
[6].Benoit Dufort, G. W. Roberts, Analog test signal generation using periodicΣΔ–encoded data streams, Kluwer Academic Publishers, 2000.
[7].M. Mahoney, “DSP-based Testing of Analog and Mixed-Signal Integrated Circuits”, IEEE Computer Society Press,1987.
[8].M. Renovell, F. Azais, S. Bernard, and Y. Bertrand, “Hardware Resource Minimization for Histogram-based ADC BIST,” Proc. of 18th IEEE VLSI Test Symposium, pp. 247 -252, 2000.
[9].F. Azais, S. Bernard, Y. Bertrand, and M. Renovell, “Implementation of a Linear Histogram BIST for ADCs,” Proc. of Design, Automation and Test in Europe, pp. 590 -595, 2001.
[10].F. Azais, S. Bernard, Y. Bertrand, and M. Renovell, “Towards an ADC BIST Scheme Using the Histogram Test Technique,” Proc. of IEEE European Test Workshop, pp. 53 -58, 2000.
[11].J.–L. Huang, C.-K. Ong, and K.-T. Cheng, “A BIST Scheme for On-chip ADC and DAC Testing,” Proc. of Design, Automation and Test in Europe Conference and Exhibition, pp. 216 –220, 2000.
[12].K. Arab, B. Kaminska, and M. Sawan, “On Chip Testing Data Converters Using Static Parameters”, IEEE Transaction on VLSI Systems, pp. 409–419, 1998.
[13].K. Arabi, B. Kaminska, and J. Rzeszut, “BIST for D/A and A/D converters,” IEEE Design & Test of Computers, pp. 40 –49, 1996.
[14].M. Ehsanian, B. Kaminska, and K. Arabi, “A New Built-In-Self-Test Approach for Digital-to-Analog and Analog-to-Digital Converters”, Proc. of International Conference Computer Aided Design, pp. 491–494, 1994.
[15].F. Xu, “A new approach for the nonlinearity test of ADCs/DACs and its application for BIST,” Proc. of European Test Workshop, pp. 34 –38, 1999.
[16].L. Benetazzo, C. Narduzzi, C. Offelli, and D. Petri, “A/D converter performance analysis by a frequency-domain approach”, IEEE Transactions on, Instrumentation and Measurement, pp. 834 –839, 1992.
[17].S. K. Sunter and N. Nagi, “A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST,” Proc. of International Test Conference, pp. 120-126, 1995.
[18].M. F. Toner and G. W. Roberts, “A BIST scheme for a SNR test of a sigma-delta ADC,” Proc. of International Test Conference, pp. 805-814, 1993.
[19].M. F. Toner and G. W. Roberts, “A BIST scheme for a SNR, Gain Tracking and Frequency Response Test of a Sigma-Delta ADC,” IEEE Transactions Circuits & Systems II , pp. -15, 1995.
[20].M. F. Toner and G. W. Roberts, “A Frequency Response, Harmonic Distortion, and Intermodulation Distortion Test for BIST of a Sigma-Delta ADC,” IEEE Trans. Circuits & Systems II , pp. 608-613, 1996.
[21].T. Kuyel, “Linearity testing issues of analog to digital converters,” Proc. of International Test Conference, pp. 747-756 , 1999
[22].G. M. Jacobs, D. J. Allstot, R. W. Brodersen, and P.R. Gray, “Design Techniques for MOS Switched Capacitor Ladder Filters,” IEEE Transactions on Circuits and Systems, pp. 1039-1044, 1978.
[23].M. S. Lee and C. Chang, “Switched-capacitor filters using the bilinear and LDI transformations,” Proc. of International Symposium Circuits and System, pp. 326-329, 1980.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
1. 二三、林立華,偵查主體概說,中興法學第二十期。
2. 二一、林一德,論共同被告之自白-最高法院八十八年度台上字第三五八四號判決之省思,萬國法律一一0期。
3. 十八、吳景芳,刑事被告緘默權之研究,中興法學第四三期。
4. 十七、何賴傑,訊問被告未全程連續錄音錄影之法律效果-評最高法院八十八年度台上字第五0七三、五七六二、六七五二號判決及台北地院八十八年度訴字第八二六號判決,月旦法學雜誌第六二期。
5. 十五、何賴傑,正當法律程序原則-刑事訴訟上一個新的法律原則,憲政時代第二五卷第四期。
6. 十四、何尚先,刑事證人訊問之法則,刑事法雜誌,第三九卷第一期。
7. 十三、余振華、康順興,檢警關係及偵查主體法制之比較考察,月旦法學雜誌第五十六期。
8. 十、史慶璞,「正當法律程序」條款與美國刑事偵審制度,輔仁法學第十四期。
9. 九、田正恆,刑事被告之沈默權,法令月刊第三九卷第二期。
10. 七、王銘勇,被告、犯罪嫌疑人緘默權之研究,全國律師一九九九年五月號。
11. 六、王梅英,淺釋證據排除法則,司法周刊第九七四期,民國八九年四月五日。
12. 五、王茂松,非任意自白之研究,中興法學第二三期。
13. 四、王茂松,傳聞法則之研究,中興法學第三十期。
14. 三、王兆鵬,證據排除法則之相關問題,刑事法雜誌第四三卷第三期。
15. 二、王兆鵬,如何確保自白之任意,全國律師民國八八年十月號。