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研究生:張瑞娟
研究生(外文):Jui-Chuan Chang
論文名稱:以預先計算為基礎之低功率全平行內容可定址記憶體設計
論文名稱(外文):Design of Low-Power Precomputation-Based Fully Parallel Content addressable Memory
指導教授:劉濱達
指導教授(外文):Bin-Da Liu
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:58
中文關鍵詞:預先計算為基礎低功率內容可定址記憶體
外文關鍵詞:Precomputation-BasedContent Addressable Memory (CAM)Low-Power
相關次數:
  • 被引用被引用:0
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  • 下載下載:50
  • 收藏至我的研究室書目清單書目收藏:1
  本論文發表一種新穎的以預先計算為基礎之全平行內容可定址記憶體架構設計,以達到低功率、低成本、低電壓及高可靠度為目的。相較於傳統的內容可定址記憶體電路設計,這種基於預先計算的設計技巧不但可以節省整個內容可定址記憶體系統中的功率消耗,亦可降低內容可定址記憶體細胞中的電晶體個數及工作電壓需求。
  在內容可定址記憶體系統中的鍵值比對電路設計,本論文採用虛擬nMOS電路設計來取代傳統的動態CMOS電路設計。採用虛擬nMOS的設計方式可以有效避免某些發生在動態CMOS電路設計上的可靠度問題。例如:電荷重新分布及漏電流等問題。以預先計算為基礎之虛擬nMOS電路設計可以大量降低靜態功率消耗問題,因此亦降低鍵值比對時的功率消耗。
  基於本論文所提出的鍵值比對電路,我們提出一個新穎的七個電晶體記憶體細胞電路,這個記憶體細胞電路不但比傳統九個電晶體電路來得簡化,且由於採用NAND型態位元比對電路取代XOR型態位元比對電路,其功率消耗亦可有效的降低。此外,為了加快位元比對速度,本論文亦提出一種高速的十個電晶體記憶體細胞電路,此電路採用NOR型態作為位元比對電路,其速度比所提出的七個電晶體電路來得快,但所需的面積亦相對增加。
  整個電路設計已在TSMC 0.35 μm SPQM CMOS的製程下製作並驗證。以一個內容大小為 128 × 30 的內容可定址記憶體,經由實際測試結果得知本論文所提出的電路架構在3.3 V的電壓供應下,工作頻率高達72 MHz (含輸出/入接腳延遲),且功率消耗低於33 mW。除此之外,由測試中亦可發現本電路在低達1.6 V的供應電壓下,工作頻率可達4 MHz。
  This paper presents a novel VLSI architecture for a fully parallel precomputation-based content addressable memory (PB-CAM) with low-power, low-cost, high-speed, and high-reliability features. This design is based on a precomputation skill that not only saves power consumption of the PB-CAM system, but also reduces transistor count and operating voltage of the PB-CAM cell.

  The proposed PB-CAM architecture adopts the static pseudo nMOS circuit design to replace the dynamic CMOS circuit design. The static pseudo nMOS circuit avoids some system reliable problems such as process violation and charge sharing.

  Based on the proposed PB-CAM architecture, a new 7-transistor memory cell circuit is proposed. In the new 7-transistor circuit, since bit comparison circuit adopts NAND type design in instead of XOR type design, the power consumption and hardware cost are largely reduced. In order to accelerate the bit comparison speed, alternative 10-transistor memory cell circuit which achieves high bit comparison speed is proposed. The hardware cost, however, is increased correspondingly.

  The whole design was fabricated with the TSMC 0.35 μm SPQM CMOS process parameters under 3.3 V supply voltage. With a 128 keys by 30 bits CAM size, the measurement results indicate that the proposed circuit works up to 72 MHz (include I/O pad delay) with the power consumption less than 33 mW. Furthermore, by the low voltage measurement results, the proposed circuit works up to 4 MHz (include I/O pad delay), and under 1.6 V supply voltage.
1.緒論…………………………………………………………………1
  1.1 背景研究……………………………………………………1
  1.2 研究動機……………………………………………………2
  1.3 論文組織……………………………………………………3

2.內容可定址記憶體架構設計………………………………………4
  2.1 內容可定址記憶體架構設計………………………………4
    2.1.1 鍵值資料寫入模式…………………………………4
    2.1.2 鍵值資料清除模式…………………………………5
    2.1.3 鍵值資料搜尋模式…………………………………5
  2.2 鍵值比對電路設計…………………………………………6
  2.3 內容可定址記憶體細胞設計………………………………10

3.以預先計算為基礎之內容可定址記憶體架構設計………………13
  3.1 預先計算為基礎之內容可定址記憶體架構………………13
  3.2 特徵值擷取電路設計………………………………………16
  3.3 預先計算為基礎之靜態式虛擬nMOS鍵值比對電路………20
  3.4 預先計算為基礎之內容可定址記憶體細胞電路…………23
  3.5 預先計算為基礎之全平行內容可定址記憶體電路………27
  3.6 範例說明……………………………………………………29

4.以預先計算為基礎之內容可定址記憶體架構實作………………33
  4.1 晶片設計流程………………………………………………33
  4.2 模擬結果……………………………………………………34
  4.3 實體佈局……………………………………………………39
  4.4 接腳定義……………………………………………………44
  4.5 操作說明……………………………………………………47
  4.6 量測結果……………………………………………………47
  4.7 討論…………………………………………………………48

5.結論與未來展望……………………………………………………52
  5.1 結論…………………………………………………………52
  5.2 未來展望……………………………………………………54
參考文獻………………………………………………………………56
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[3]H. Yamada, Y. Murata, T. Maeda, R. Ikeda, K. Motohashi, and K. Takahashi, “Real-time string search engine LSI for 800-Mbit/s LANs,” in Proc. IEEE 1988 Custom Integrated Circuits Conf., 1988, pp. 21.6.1-21.6.4.

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[13] S. V. Kartalopoulos, “Associative RAM-based CAM applicable to packet-based broadband systems,” in Proc. IEEE GLOBECOM, Nov. 1998, pp. 2888-2891.

[14] R. Djwmal, G. Mazare, and G. Michel, “Toward reconfigurable associative architecture for high speed communication operators,” in Proc. IEEE ECBS, Mar. 1996, pp. 74-79.

[15] C. A. Zukowski and S. Y. Wang, “Use of selective precharge for low-power on the match lines of content-addressable memories,” in Proc. IEEE MTDT, Aug. 1997, pp. 64-68.

[16] C. A. Zukowshi and S. Y. Wang, “Use of selective precharge for low-power content-addressable memories,” in Proc. IEEE ISCAS, June 1997, pp. 1788-1791.

[17] I. Y. L. Hsiao, D. H. Wang, and C. W. Jen, “Power modeling and low-power design of content addressable memories,” in Proc. IEEE ISCAS, May 2001, pp. 926-929.

[18] G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, “A novel low power CAM design,” in Proc. IEEE ASIC/SOC Conf., Sept. 2001, pp. 198-202.

[19] F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, “Fully parallel 30-MHz, 2.5Mb CAM,” IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1690-1696, Nov. 1998.

[20] J. P. Wade and C. G. Sodini, “A ternary content-addressable search engine,” IEEE J. Solid-State Circuits, vol. 24, pp. 1003-1013, Aug. 1989.

[21] H. Higuchi, S. Tachibana, M. Minami, and T. Nagano, “A 2-ns, 5-mW, synchronous-powered static-circuit fully associative TLB,” in Proc. IEEE Symp. VLSI Circuits Dig. Tech. Papers, June 1995, pp. 21-22.

[22] H. Bergh, J. Eneland, and L. Lundström, “A fault-tolerant associative memory with high-speed operation,” IEEE J. Solid-State Circuits, vol. 25, pp. 912-919, Aug. 1990.

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[24] P. F. Lin and J. B. Kuo, “A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell,” IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 666-675, Apr. 2001.

[25] S. Jones, “Design, selection and implementation of a content-addressable memory for a VLSI CMOS chip architecture,” in Proc. IEE Comput. Digit. Tech., vol. 135, pp. 165-172, May 1988.

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[27] T. Hanyu, N. Kanagawa, and M. Kameyama, “One-transistor-cell multiple-valued CAM for a collision detection VLSI processor,” in ISSCC Dig. Tech. Papers, Feb. 1996, pp. 264-265, 457.

[28] T. Miw, H. Yamada, Y. Hirota, T. Satoh, and H. Hara, “A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies”, IEEE J. Solid-State Circuit, vol. 31, no. 11, pp. 1601-1609, Nov., 1996.

[29] K. Ishibashi, K. Komiyaji, H. Toyoshima, M. Minami, N. Ohki, H. Ishida, T. Yamanaka, T. Nagano, and T. Nishida, “A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL,” IEEE J. Solid-State Circuits, vol. 30, pp. 1189-1195, Nov. 1995.

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[31] K. Roy and S. C. Prasad, Low-Power CMOS VLSI Circuit Design. New York: Wiley, 2000.K. J. Schultz and P. G. Gulak, “Architectures for large-capacity CAMs,” Integration, the VLSI Journal, vol. 18, pp. 151-171, 1995.

[32] C. S. Lin, J. C. Chang, and B. D. Liu, “Design for low-power, low-cost, and high-reliability precomputation-based content addressable memory,” will be presented at the APCCAS 2002. (Oct. 28-31. 2002, Bali, Indonesia)
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