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研究生:李芳明
研究生(外文):Fan-Min Li
論文名稱:語音轉語音翻譯系統晶片設計
論文名稱(外文):SOC Design for Speech to Speech Translation
指導教授:王駿發
指導教授(外文):Jhing-Fa Wang
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:85
中文關鍵詞:動態可程式規劃內嵌型例句式翻譯
外文關鍵詞:Track BackTemplate Search
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  • 被引用被引用:3
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  • 下載下載:126
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近年來由於行動資訊服務已蔚為風行,使得語音轉語音(口語)翻譯研究日益興盛,目前相關研究成果有由德國工業前瞻技術中心開發的一套(Server-based) Verbmobile系統,透過語音辨識、語言翻譯及語音合成來循序(serial)處理語音對語音的轉譯,使用者可藉由手機、電話、網際網路與此系統聯繫並進行跨語言的對談。唯此系統需建立在電腦伺服器之上,無法隨處可用及隨時可用,所以在本研究中研發具可攜性之語音轉語音翻譯系統單晶片,有效克服此問題,並可移植在各種多媒體人機介面應用上。
在語音翻譯演算法研發的過程中,由於語音辨識上無法達到百分之百的辨識率,故把語音辨識內嵌(Embedded)於語言翻譯合併處理,而例句式(template-based)語言翻譯是現今主要翻譯技術,其目的是搜尋與輸入句最相似的例句,將比對相異之處再作翻譯後處理調整(Insertion、Deletion和Replacement),所以本研究中直接將語音信號透過動態規劃(one-stage)搜尋作例句比對與翻譯,並於個人電腦驗證其演算法之可行性,透過修正後的動態規劃演算法,其實驗結果可達8成至9成的轉譯正確率。
在其晶片設計方面,硬體架構採SOC之設計理念,除了利用既有的IP外,由於目前搜尋比對相關研究之參考模組大小為固定式,故在研究中亦根據系統需求,特別研發出可適用在變動式動態規劃例句搜尋IP與路徑回溯IP。在ASIC驗證方面,整合例句搜尋IP與路徑回溯IP於單晶片架構中,並利用雙記憶體模組電路設計,使得例句搜尋和路徑回溯處理可同步進行,如此不僅減少閒置元件使用,亦可加快運算速度。
最後,在此研究中不僅完成國台英口語翻譯IC系統晶片架構設計,在適度的Design Reuse及修改之下,亦可應用於跨國電話語音聯繫、觀光旅遊溝通輔助、個人數位助理 (PDA)、影視多語選擇及語言學習等領域中,為這些領域添色不少。
In the past few years, mobile information services have been applied to many communication systems. And more and more people have devoted themselves to the research of speech-to-speech translation (also called spoken language translation). Recently, German Federal Ministry for Education and Research develops a server-based system called Verbmobile, which works through recognition, translation, and synthesis to process the speech transformation. Users first make communication with the system through cell phone, telephone or the Internet. Then they are able to talk to each other using their own languages. However, the system is not real-time and portable. It is built in the local computer server. Therefore, the main goal of this research is to develop the real-time speech-to-speech translation system in SOC (system on a chip). People who speak different kinds of languages could communicate well with the chip spontaneously.
For developing the speech-to-speech translation algorithm, we decide to integrate recognition into language translation because of the defective recognition method. The template-based language translation is the main paradigmatic approach for spoken language translation. The goal of this approach is to search the most similar example sentence of the input sentence and to make post-editing (Insertion, Deletion and Replacement) of the found example. Therefore, we introduce a dynamic programming search algorithm for template-based spoken language translation, and verify the proposed algorithm in PC. In our experiments, the correct percentage of template-based translation ranges from 80% to 90%.
For the design of the chip, we introduce the SOC design tactic. We not only use elementary IP but also study new variable dynamic programming designs for template-search IP and trace-back IP in our research. In the ASIC verification, we combine the template-search IP and track-back IP in a single chip. In addition, we use a double RAM circuit design, which not only execute template search process and trace back process synchronously but also reduce unused components to improve the computation performance.
In conclusion, this research not only completes the framework of Mandarin, Taiwanese, and English translation system IC design. With proper Design-Reuse and modification, it can also be used in multi-national speech communication, touristy assistance, PDA, TV multi-language selection, language learning, and so forth. This has achieved a remarkable progress in these fields.
中文摘要………………………………………………………………….i
英文摘要…………………………………………………………………ii
誌謝..………………………………………………………………….…iii
目錄………………………………...……………………………………iv
圖目錄…………………………………………………………………...vi
表目錄…………………………………………………………………...ix
中文摘要 i
Abstract ii
第一章 緒論 1
1-1 研究動機 1
1-2 研究背景 2
1-3 章節概要 3
第二章 語音轉語音翻譯系統 4
2-1 系統簡介 4
2-1.1 循序型(Serial)系統 5
2-1.2 內嵌型(Embedded)系統 8
2-1.3 機器翻譯(MT)類型 9
2-1.4 例句式翻譯(EBMT)系統 11
2-2 內嵌型例句式翻譯系統 12
2-2.1 語句特徵參數擷取 14
2-2.2 動態規劃式例句比對演算法(One-Stage) 16
2-2.3 語句後處理調整 23
2-3 軟體模擬與實驗討論 26
第三章 翻譯晶片架構設計 34
3-1 系統晶片整合架構 34
3-2 固定式動態規劃比對架構 37
3-2.1 Viterbi動態規劃解碼架構探討 37
3-2.2 BNN建階式比對架構探討 40
3-2.3 One-Stage架構問題討論 43
3-3 變動式One-Stage架構設計 45
3-3.1 失真量累積單元(Distortion unit)設計 48
3-3.2 串列輸入/並列輸出單元(SIPO unit)設計 49
3-3.3 處理單元(PE unit)設計 50
3-3.4 One-Stage各單元整合架構 51
3-3.5 One-Stage之有限狀態機設計 52
3-4 變動式路徑回溯架構設計 58
3-4.1 Double RAM路徑回溯電路 58
3-4.2 路徑回溯之有限狀態機設計 59
第四章 晶片驗證與模擬 66
4-1 時序圖 67
4-2 系統規格 68
4-3 One-Stage各單元模擬結果 70
4-3.1 失真量累積單元(Distortion unit) 70
4-3.2 串列輸入/並列輸出單元(SIPO unit) 71
4-3.3 處理單元(PE unit) 72
4-3.4 路徑回溯解碼單元(TD unit) 73
4-4 晶片製作 75
第五章 結論與未來展望 78
參考文獻……………………………………….……………………….80
自述…………………………………………….……………………….85
軟體演算法
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硬體晶片架構
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