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研究生:洪郁庭
研究生(外文):Yu-Ting Hung
論文名稱:利用嵌入式處理器控制之單晶片系統測試平臺
論文名稱(外文):An Embedded-Processor-Driven Platform for SOC Testing
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:70
中文關鍵詞:易測性電路設計嵌入式處理器系統單晶片測試內建式自我測試電路
外文關鍵詞:embedded processorDFTBISTSOC Testing
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隨著積體電路製程的進步,以核心電路為基礎的單晶片系統設計方式逐漸成為IC設計產業中一個引人注目的趨勢。該設計方法具有提高晶片效能、縮短設計時程及降低製造成本等多項優點。然而,這樣的方式也帶來了許多新的挑戰,最嚴重的問題之一就是該如何測試此種單晶片系統。因此本論文提出一個利用嵌入式處理器控制的單晶片系統測試平臺來解決此種晶片的測試問題。
在所提出的測試平臺中,我們利用在單晶片系統中原本就存在的嵌入式處理器來執行一個測試程式藉以控制整個測試流程。這個測試程式藉由一些輔助電路的幫助,會對晶片中的核心電路進行結構性測試(structural testing)。本測試平臺可以測試那些加入如Boundary Scan或IEEE P1500之易測性設計的各種核心電路。此外,由於本測試平臺的內部元件採用了標準化的介面,所以可以應用在各類型的單晶片系統上。與近來所提出的各種單晶片系統測試架構比較,我們所提出的測試平臺減輕了對昂貴測試機台的需求,也因此大幅減少了測試成本。
為了驗証該測試平臺的實用性,我們設計了一個以ARM7處理器作為內嵌式處理器的單晶片系統電路,而其系統匯流排採用了AMBA AHB。實驗結果顯示出該單晶片系統測試平臺提供了一個可行的方法可用以解決單晶片系統的測試問題。
With the progress in VLSI technology, the core-based system-on-chip (SOC) design methodology is becoming an attractive solution in the IC design industry for its higher performance, shorter design time, and lower manufacturing cost. However, the SOC design also introduces many new challenges. One of the most critical problems is the testing of an SOC. In this thesis, an embedded-processor-driven platform for SOC testing is developed.
In this platform, an embedded processor in the SOC under test is employed as the control kernel to execute a test program. This program handles the structural testing of the IP cores in the SOC with the assistance of some extra circuitry. The platform supports the testing of cores that are wrapped by the standardized boundary scan wrappers or the IEEE P1500 wrappers. With a standardized interface, the proposed platform can be applied to different kinds of SOC designs of diverse functions. Compared with the test access mechanisms proposed recently, our methodology alleviates the need of expensive automatic test equipment, and hence can greatly reduce the total test cost.
To verify the practicability of the platform, an ARM-based SOC chip is developed with an ARM7 core as the embedded processor and an AMBA AHB bus as the backbone bus. Experimental results show the proposed platform is a feasible solution to the SOC test problem.
Chapter 1 INTRODUCTION 1
1.1. MOTIVATION 1
1.2. INTRODUCTION OF PROPOSED SOC TEST PLATFORM 2
1.3. ORGANIZATION OF THESIS 3
Chapter 2 BACKGROUND AND PREVIOUS WORK 5
2.1. BACKGROUND 5
2.1.1. Concepts of Core-based SOC Testing 5
2.1.2. IEEE P1500 Standard 7
2.2. PREVIOUS WORK 11
2.2.1. Functional Testing for Processor 11
2.2.2. Processor-based Test Methodologies 13
Chapter 3 AN EMBEDDED-PROCESSOR-DRIVEN SOC TEST PLATFORM 16
3.1. FEATURES 16
3.2. COMPONENTS 17
3.3. PLATFORM OPERATION 19
3.4. TEST FLOW 22
Chapter 4 TEST PLATFORM IMPLEMENTATION 24
4.1. IMPLEMENTATION OVERVIEW AND PROCEDURES 24
4.2. P1500 WRAPPER INSERTION 26
4.3. DESIGN OF TAM CONTROLLER 27
4.3.1. TAM Controller Overview 27
4.3.2. Data Registers 30
4.3.3. Memory Access Control 33
4.3.4. Shift Mechanism 33
4.3.5. TMS Generator 37
4.3.6. Multiple-Input Signature Register (MISR) 39
4.3.7. Peripheral VCI 40
4.4. TEST BUS AND TAM INTEGRATION 41
4.5. SOFTWARE: TEST PROGRAM AND TEST DATA TRANSFORMATION 42
4.5.1. Test Program 42
4.5.2. Test Data Transformation 44
4.6. ILLUSTRATIVE REVIEW OF PLATFORM OPERATION 45
Chapter 5 CASE STUDY 50
5.1. BACKGROUND 50
5.1.1. ARM7 Microprocessor 50
5.1.2. Advanced High-performance Bus (AHB) of AMBA 53
5.2. TEST CHIP: AN ARM-BASED SYSTEM 55
5.2.1. Architecture 55
5.2.2. Test Program and Test Data 57
5.3. EXPERIMENTAL RESULTS 59
5.3.1. Simulation Results 59
5.3.2. Statistics of the Sample SOC 63
Chapter 6 CONCLUSIONS AND FUTURE WORK 66
6.1. CONCLUSIONS 66
6.2. FUTURE WORK 67
REFERENCES 68
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[8]R. Kapur, B. Keller, B. Koenemann, M. Lousberg, P. Reuter, T. Taylor, and P. Varma, “P1500-CTL: Towards a Standard Core Test Language,” in Proc. VLSI Test Symposium, pages 489-490, 1999.
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[13]A.J. van de Goor, T.J.W. Verhallen, “Functional Testing of Current Microprocessors (applied to the Intel i860),” in Proc. International Test Conference, page 684, 1992.
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[15]L. Chen and S. Dey, “DEFUSE: A Deterministic Functional Self-Test Methodology for Processors,” in Proc. VLSI Test Symposium, pages 255-262, 2000.
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[17]W.-C. Lai, A. Krstic, and K.-T. Cheng, “Test Program Synthesis for Path Delay Faults in Microprocessor,” in Proc. International Test Conference, pages 1080-1089, 2000.
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[19]W.-C. Lai and K.-T. Cheng, “Instruction-level DfT for testing processor and IP cores in system-on-a-chip,” in Proc. Design Automation Conference, pages 59-64, 2001.
[20]C.-H. Tsai and C.-W. Wu, “Processor-programmable memory BIST for bus-connected embedded memories,” in Proc. Design Automation Conference, pages 325-330, 2001.
[21]J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, “Processor-based built-in self-test for embedded DRAM,” IEEE Journal of Solid-State Circuits, pages 1731-1740, Nov. 1998
[22]R. Rajsuman, “Testing a System-On-a-Chip with Embedded Microprocessor,” in Proc. International Test Conference, pages 499-508, 1999.
[23]J.-R. Huang, M.K. Iyer, and K.-T. Cheng, “A self-test methodology for IP cores in bus-based programmable SoCs,” in Proc. VLSI Test Symposium, pages 198-203, 2001.
[24]C.A. Papachristou, F. Martin, and M. Nourani, “Microprocessor based testing for core-based system on chip,” in Proc. Design Automation Conference, pages 586-591, 1999.
[25]M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing,” Kluwer Academic Publishers, 2000.
[26]SynTest Technology, Inc., TurboScan User Guide, http://www.syntest.com/.
[27]SynTest Technology, Inc., TurboBIST-Memory User Guide, http://www.syntest.com/.
[28]“The Source For Perl,” http://www.perl.com.
[29]VSI Alliance On-Chip Bus Development Working Group. “Virtual Component Interface Standard (OCB 2 2.0),” April 2001.
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[31]PCI Special Interest Group, Hillsboro, Oregon, USA. PCI Local Bus Specification, Revision 2.0, April 1994.
[32]ARM7 Data Sheet, http://www.arm.com.
[33]AMBA Specification, http://www.arm.com.
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