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研究生:曾南欣
研究生(外文):Nan-Hsin Tseng
論文名稱:系統單晶片中多類型內嵌同步記憶體之萬用內建式自我測試電路
論文名稱(外文):Universal BIST for Heterogeneous Embedded Synchronous Memory cores in SOC
指導教授:李昆忠李昆忠引用關係
指導教授(外文):Kuen-Jong Lee
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:英文
論文頁數:73
中文關鍵詞:同步式記憶體內建式自我測試電路系統單晶片
外文關鍵詞:SOCSynchronous MemoryBIST
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由於嵌入式記憶體在系統單晶片上所佔的面積逐漸增加及多樣化的趨勢,使得嵌入式記憶體的測試問題漸漸的也成為了十分重要的課題。低成本及易測性的因素,使自我測試架構則成為目前最為廣泛使用在嵌入式記憶體的測試。因此,在本論文中為了節省嵌入式記憶體自我測試架構在系統單晶片上的面積,而提出了多類型內嵌同步記憶體之萬用內建式自我測試電路,用以測試系統單晶片上的同步靜態隨機存取記憶體、同步動態隨機存取記憶體、雙倍資料速率同步動態隨機存取記憶體及同步快閃記憶體。

行進式測試演算法(march testing algorithm)是以循序方式進行對各個記憶體元件進行測試,因此行進式測試演算法廣泛應用於系統單晶片之嵌入式記憶體及獨立型記憶體的測試。我們首先進行分析並設計一個電路架構藉著簡單控制信號來產生行進式測試樣式(pattern)以降低硬體成本。此一電路整合了四十二個行進式測試演算法設計於單一電路架構中,如此將具有低成本及易操作使用等優點。此外,這個自我測試電路也利用Data Background的選擇信號來產生所要寫入、讀出記憶體的資料,去搭配不同的行進式測試演算法,以增加錯誤涵蓋率。其次為了能廣泛地應用於測試各式各樣的不同類型同步記憶體上,測試向量產生器及記憶體命令產生器的設計成為本論文的另一重點。為了解決不同架構的記憶體所需的各種命令程序,我們提出一個混合型的測試向量產生器及記憶體命令產生器架構,在同步時脈的基礎之下,可以產生用以控制各類型同步記憶體的命令程序。由於這樣的設計,可以讓使用者依據不同的需求來進行測試工作,以減輕內建式自我測試的面積負擔。
Due to the drastic growing up and heterogeneity of embedded memory cores in SOCs, the memory testing issue has become a major problem in the SOC testing. For low cost and testability consideration, BIST is a widely accepted methodology for testing embedded memories within SOCs. In this thesis, we propose a universal BIST design for the heterogeneous embedded memory cores in an SOC. The memory cores considered include Sync-SRAM, SDRAM, DDR SDRAM and Sync-Flash.
Because the memory cells can be tested in a regular address order, the March algorithms are popular to test the embedded memory cores of the SOC and stand-alone memories. In our design, we first propose a Universal Test Instruction Generator. We analyze the properties of March algorithms and use an efficient procedure to reduce the memory storage for these characteristics. The proposed approach integrates 42 existing march algorithms into an embedded test instruction generator. This generator is capable of executing any March algorithm with small area overhead. To deal with word-oriented memory cores, we also use a “background” signal to select different data backgrounds for memory cells. Besides, to test manifold memory cores in an SOC, different test command sequences are necessary. A mixed-type test vector generator and a command generator are proposed to generate the command sequences. According to this proposed design, the user can test heterogeneous memory cores in an SOC using a single BIST controller and hence can significantly reduce the BIST hardware overhead.
Chapter 1 Introduction 1
1.1 The importance of embedded memory to SOC 1
1.2 Embedded memory advantages 3
1.3 Why Memory BIST ? 4
1.4 The contributions and novelties of this thesis 5
1.5 Organization of this thesis 6
Chapter 2 Data Backgrounds and Previous Work 7
2.1 Synchronous Memory Introduction 7
2.1.1 Synchronous SRAM 7
2.1.2 SDRAM & DDR SDRAM 9
2.1.3 Synchronous FLASH 16
2.2 Memory Fault Models 22
2.3 March-based Memory Testing Algorithms 25
Chapter 3 BIST Circuit Architecture 30
3.1 Architecture of Synchronous Memory BIST 31
3.2 Universal Test Instruction Generator 35
3.2.1 Architecture Description 35
3.2.1 Reduction procedure of Algorithm steps 36
3.3 Test Control Vector Generator 40
3.4 Command & Address Generator 47

Chapter 4 Simulation Results 52
4.1 The simulation results of Instruction Generator 52
4.2 The simulation results of SDRAM & DDR SDRAM 55
4.3 The simulation results of Sync-Flash 61
Chapter 5 Conclusions 67
5.1 Summary 67
5.2 Conclusions 69
References 70
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[2]B. Lu, “Embedded DRAM”, Infineon Technologies, 2000.

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[4]D. Barkin, “Built-in test for large DRAM chips”, Compilers and Computer Architecture , 1997.

[5]A. K. Sharma, Semiconductor Memories : Technology, Testing, and Reliability, IEEE Press, Piscataway, 1997.

[6]B. Prince, Semiconductor Memories: A Handbook of Design, Manufacture and Application, John Wiley & Sons, Chichester, UK, 1991.

[7]Micron Technology Synchronous SRAM datasheet, http://www.micron.com, 2001.

[8]Micron Technology Synchronous DRAM datasheet, http://www.micron.com, 2001.

[9]Micron Technology DDR SDRAM datasheet, http://www.micron.com, 2001.

[10]P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells—an overview”, Proc. of the IEEE, vol. 85, no. 8, Aug. 1997, pp. 1248–1271.

[11]Micron Technology SyncFlash datasheet, http://www.micron.com, 2001.
[12]A. J. van de Goor, Testing Semiconductor Memories: Theory and Practice, John Wiley & Sons, Chichester, UK, 1991.

[13]S. Aritome, R. Shirota, G. Hemink, T. Endoh, and F. Mausouka, “Reliability issues of flash memory cells”, Proc. of the IEEE, vol. 81, no. 5, May 1993, pp. 776–787.

[14]M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing flash memories”, in Proc. 13th Int. Conf. VLSI Design, Jan. 2000, pp. 406–411.

[15]M. Mohammad and K. K. Saluja, “Flash memory disturbances: modeling and test”, in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 218 –224.

[16]IEEE, IEEE 1005 Standard Definitions and Characterization of Floating Gate Semiconductor Arrays, IEEE Standards Department, Piscataway, 1999.

[17]J.C. Yeh, C.F. Wu, K.L. Cheng, Y.F. Chou, C.T. Huang, and C.W. Wu, “Flash Memory Built-In Self-Test Using March-Like Algorithms”, in Proc. IEEE Int. Workshop on EDELTA, Christchurch, Jan. 2002, pp. 137-141.

[18]V. Yarmolik, Y. Klimets, and S. Demidenko, "March PS (23N) Test for DRAM Pattern-Sensitive Faults," Proc. of 7th Asian Test Symp., Singapore, December 1998, pp. 354-357.

[19]A. J. van de Goor, "Using March Tests to Test SRAMs," IEEE Design and Test of Computers, March 1993, pp. 8-14.

[20]A. J. van de Goor and G. N. Gaydadjiev, “March U: A Test for Unlinked Memory Faults,” IEE Proc. - Circuits Devices Syst., Vol. 144, No. 3, June 1997, pp. 155-160.

[21]A. J. van de Goor, G. N. Gaydadjiev, V. N. Yarmolik, and V. G. Mikitjuk, “March LR: A Test for Realistic Linked Faults,” Proc. of European Design and Test Conf., 1997, p. 627.

[22]O. Kebichi, M. Nicolaidis, and V. N. Yarmolik, “Exact Aliasing Computation for RAM BIST,” Proc. of Int’l Test Conf., 1995, pp. 13-22.

[23]A. J. van de Goor and Y. Zorian, “Effective March algorithms for Testing Single-Order Addressed Memories,” Proc. of European Conference on Design Automation with the European Event in ASIC Design, 1993, pp. 499-505.

[24]A. J. van de Goor, G. N. Gaydadjiev, V. N. Yarmolik, and V. G. Mikitjuk, “March LR: A Test for Realistic Linked Faults,” Proc. of 14th VLSI Test Symposium, 1996, pp. 272-280.

[25]A. J. van de Goor and A. Offerman, “Towards a Uniform Notation for Memory Tests,” Proc. of European Design and Test Conf., 1996, pp. 420-427.

[26]V. G. Mikitjuk, V. N. Yarmolik, and A.J. van de Goor, “RAM Testing Algorithms for Detecting Multiple Linked Faults,” Proc. of European Design and Test Conf., 1996, pp. 435-439.

[27]W. X. Hu, “ Built-In Self Test Circuit Design for SDRAM”, Master Thesis, Dept. of E.E., NCKU, Taiwan, June, 2000.

[28]W. L. Wang, K. J. Lee, and J. F. Wang, “An On-Chip March Pattern Generator For Testing Embedded Memory Cores”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 5, Oct. 2001, pp. 730-735.


[29]W. L. Wang, K. J. Lee, and J. F. Wang, “A Universal March Pattern Generator for Testing Embedded Memory Cores”, Proceedings of 12th Annual IEEE ASIC/SOC Conference, 1999, pp. 228-232.

[30]W. L. Wang, K. J. Lee, “Fast Deterministic Test Pattern Generation for Scan-Based BIST Environment,” Journal of Chinese Institute of Electrical Engineering, Vol. 8, No. 4, Nov. 2001, pp. 365-376.

[31]W. L. Wang, K. J. Lee and J. F. Wang, “An Embedded March algorithm Test Pattern Generator for Memory Testing,” Proceedings of International Symposium on VLSI Technology, Systems, and Applications, 1999, pp. 211–214.
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