臺灣博碩士論文加值系統

本論文是於德儀TMS320C6x數位訊號處理(DSP)晶片以實現雙通道之MPEG-4簡易版視訊壓縮及解壓縮標準為目標。主要研究工作著重於C6x平台的實現及其視訊電路設計，並對MPEG-4標準於C6x之效能評估及針對其缺點提出程式最佳化與改善。為了改進系統的程式效能，我們提出了一個適用於C6x指令架構下之非等長碼解碼方式，該解碼方式使解壓縮端的非等長碼解碼能更加簡單快速。而本論文的另一個重點是使用FPGA晶片設計視訊介面電路以分擔C6x晶片於影像擷取的負擔，使其能專注於壓縮與解壓縮的工作，以達到最有效運用C6x晶片，並完成MPEG-4即時壓縮與解壓縮標準的目標.

In this thesis, we plan to realize the MPEG-4 simple profile video compression standard on Texas Instruments TMS320C6x Digital Signal Processing (DSP) chips figured with two-channel video signals. The major research works include the video compression software realization in the C6x DSP chip and the design of two-channel video interface circuit. The performance evaluation after porting the MPEG-4 video compression software in the C6x DSP is first achieved. Based on its vulnerability, we then improve and optimize its software implementation by using C6x software pipeline programming techniques. To advance its speed, we further propose a fast VLC decoding method, which decodes two codewords at each decoding loop in C6x platform. Another important contribution to this research is that we successfully design a video input and output interface circuit, which reduces the C6x loads in capture of image data. The realized video system shows that the realized interface circuit in a FPGA chip helps the C6x to concentrate its computation power on coding tasks such that the real-time MPEG-4 coding system can be archived.

1.簡介..........................................1
1.1影像通訊的發展...............................1
1.2影像壓縮標準的現況...........................1
1.3影像壓縮標準的實現...........................2
1.4 DSP的選擇與量……………………………………….3
1.5論文綱………………………………………………….4
2.MPEG-4 視訊壓縮系統於C6x平台之實現............5
2.1簡介.........................................5
2.2 MPEG-4壓縮及解壓縮之架構…………………………6
2.3 於TI C6711晶片上之實現......................9
2.4 程式之最佳化及加速.........................17
3. C6x指令架構下之快速非等長碼解碼.............30
3.1 簡介.......................................30
3.2 快速非等長碼解碼法.........................32
3.3運用查表法之快速解法………………………………35
4. C6x視訊系統週邊硬體之設計...................44
4.1 簡介………………………………………………….44
4.2 系統概述…………………………………………….44
4.3 影像輸入元件及資料格式………………………….47
4.4 影像訊號的分離與儲存…………………………….49
4.5 SDRAM寫入程序之管理........................52
4.6 SDRAM的畫面記憶體管理......................54
4.7 DSP非同步介面的傳輸………………………………57
4.8 效能與分析………………………………………….62
4.9與德州儀器之ITDK系統之比較…………………… .64
4.10 結論......................................66
5. 結論........................................67
參考文獻.......................................68

[1] ISO/IEC JTC1/SC29/WG11, “ISO/IEC CD 13818 : information technology,”MPEG-2 Committee Draft, Dec.1993.[2]International Telecommunication Union, “Video coding for low bit-rate communication,” ITU-T Recommendation H.263,July.1995.[3] “MPEG-4 Video Verification Model version 18.0”, ISO/IEC JTC1/SC29/WG11 N3908,January 2001.[4] J. H. Li and Nam Ling, “Architecture and Bus-Arbitration Scheme for MPEG-2 Video Decoder” IEEE trans. Circuit and Syst. for video Tech., vol 9 , pp 727-731, AUG 1999.[5] Shahriar M Akramullah, Ishfaq Ahmad and M.L. Liou “Optimization of H.263 Video Encoder Using a single Processor Computer: Performance Tradeoff and Benchmarking” IEEE trans. Circuit and Syst. for video Tech., vol 11 , NO.8, AUG 2001.[6]TMS320C6000 Optimizing Compiler User’s Guide. Texas Instrument Incorporated 1997.[7]TMS320C6000 Assembly Language Tools User’s Guide. Texas Instrument Incorporated 1997. [8]TMS320C6000 Code Optimization: Inner Loop or Outer Loop Performance Tradeoff .Texas Instrument Incorporated 1998. [9]TMS320C6000 Optimizing C compiler .Texas Instrument Incorporated 1998.[10]D.S.Ma, J.F.Yang, and J.Y.Lee “Programmable and Parallel Variable -Length Decoder for Video Systems”, IEEE Transactions on Consumer Electronics , vol.39, No.3, AUG 1993.[11]TMS320C6000 EMIF To External Asynchronous Interface . Texas Instrument Incorporated 1997.