跳到主要內容

臺灣博碩士論文加值系統

(54.80.249.22) 您好!臺灣時間:2022/01/20 06:37
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:古濱鴻
研究生(外文):Pin-Hung Ku
論文名稱:具有高速乙太網路單元之186相容處理器單晶片系統設計
論文名稱(外文):A Single Chip Design of a 186 Compatible Embedded Processor with Fast Ethernet MAC unit
指導教授:陳中和陳中和引用關係
指導教授(外文):Chung-Ho Chen
學位類別:碩士
校院名稱:國立成功大學
系所名稱:電機工程學系碩博士班
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2002
畢業學年度:90
語文別:中文
論文頁數:72
中文關鍵詞:高速乙太網路
外文關鍵詞:Ethernet
相關次數:
  • 被引用被引用:0
  • 點閱點閱:196
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0

隨著網際網路的廣泛應用,單單具有處理、運算的功能,已經不敷使用,所以本論文研製了一個符合IEEE 802.3 CSMA/CD protocol 乙太網路存取介面的186相容指令之嵌入式單晶片處理器,由於這個單晶片是屬於嵌入式的微處理器,所以乙太網路媒介存取控制晶片,可以傳送直接來自晶片上週邊匯流排欲傳送的資料封包經由MII介面,再傳送到實體層,相反地,則是接受由實體層到MII介面的封包資料,乙太網路存取控制再透過晶片週邊匯流排將資料搬移到系統記憶體中。
在我們的設計中,首先我們先設計一個符合IEEE 802.3標準,同時支援半雙工與全雙工傳送與接收模式的控制晶片,特別是我們在傳送與接收端各配置了二千個位元組的先入先出的記憶體,以為了避免晶片週邊匯流排的頻寬消耗。接著我們將這個乙太網路存取控制晶片整合入一個嵌入式微處理器中,使之成為一個系統單晶片,透過嵌入式微處理器中的直接記憶體存取控制器與中斷控制器,緊緊的整合運作。然後我們以硬體與軟體共同驗證的方式尋找出硬體與軟體的相依性,並將我們的驅動程式載入full HDL system model中,更精確的來驗證我們所製作的系統單晶片。最後經由FPGA demo board,透過實際的網路傳輸線,驗證MAC unit 封包傳送與接收的正確性。


In this thesis, we present a single chip design of a 186 compatible embedded processor with fast Ethernet MAC unit that complies with IEEE 802.3 CSMA/CD protocol. On transmitting, this chip aggregated a valid data frame from the On-chip Peripheral Bus (OPB) to Media Independent Interface (MII) and passed to Physical Layer (PHY). On receiving, the PHY assembled the serial data and passed it to MII. The MAC unit assembled the nibble data into an FIFO and passed it to system memory by the OPB.
We design a MAC unit that supports both full duplex and half duplex mode to transmit and receive frame data. It also supports flow control mode that complies with IEEE 802.3 standard. In order to save OPB bandwidth, we put 2K-byte FIFO into transmit and receive block respectively. Through the DMA controller and interrupt controller of the embedded processor, the MAC unit is incorporated tightly with the processor. Then we look for the dependencies between the hardware and software by hardware/software co-verification model. We put all of our hardware and software designs into a full HDL system model for verification. At last, we use FPGA demo board to transmit and receive frame data through the physical layer chip to verify our design.
The thesis describes the architecture of the processor and media access control protocol of the Ethernet MAC unit. Finally, we show the simulation result and evaluation analysis and implementation result.


Chapter 1.序論1
1.1 緣起1
1.2 動機與目標1
1.3 本篇論文之貢獻2
1.4 章節介紹2
Chapter 2.背景知識介紹3
2.1 MAC frame structure3
2.2 CSMA/CD Media Access Control 精確描述5
2.2.1 IEEE 802.3 CSMA/CD 組織架構5
2.2.2 Frame transmit process6
2.2.3 Bit transmit process9
2.2.4 Frame receive process10
2.2.5 Bit receive process12
2.3 流量控制13
2.3.1 Pause Frame 描述13
2.3.2 Pause frame format14
2.4 如何設計一個SOC單晶系統14
2.5 總結17
Chapter 3.系統設計18
3.1 系統架構18
3.2 Ethernet MAC Architecture19
3.2.1 Host Interface20
3.2.2 Media independent interface21
3.3 Function description22
3.3.1 Tx MAC block22
3.3.2 Rx MAC block26
3.3.3 Flow control block29
3.3.4 Station management block32
3.3.5 FIFO block34
3.3.6 Control/Status Registers Block35
3.4 如何讓MAC unit動作43
3.5 總結44
Chapter 4.系統實作的方法以及成果45
4.1 SOC challenges45
4.1.1 Test Methodologies45
4.1.2 Co-verification models46
4.2 MAC device driver48
4.3 Function simulation50
4.3.1 Tx MAC and host interface51
4.3.2 Transmit frame52
4.3.3 Transmission in half-duplex with collision54
4.3.4 Receive frame55
4.3.5 Rx MAC and host interface57
4.3.6 Receive frame with address error58
4.3.7 Receive frame with FCS error59
4.3.8 Receive frame with RXERR error60
4.3.9 Control frame61
4.4 Verification65
4.4.1 Implementation flow65
4.4.2 Gate count66
4.5 FPGA Prototyping66
4.5.1 環境設定與封包內容67
4.6 總結68
Chapter 5.結語與未來工作69
5.1 結語69
5.2 未來工作69


References[1] IEEE Std.802.3, 1998 Edition.[2] Advances Micro Devices , “Am186ES/ESLV and Am188 ES/ESLV,” Data Sheet, Feb. 2000[3] Samsung Electronics, “KS32C50100 High Performance Network Controller,” Users Manual, Feb. 2000.[4] Jing-Fei Ren and R. Landry,“Flow Control and Congestion Avoidance in Switched Ethernet LANs,” Communications, 1997. ICC '97 Montreal, Towards the Knowledge Millennium. 1997 IEEE International Conference on , Vol. 1 , 1997.[5] C. H. Chen, M. H. Sheu, M. D. Shieh, T. S. Li, and M. C. Chen, “Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,” Proceeding of the IEEE Asia Pacific Conference on Communications, 1998.[6] M. H. Shue, C. H. Chen, M. D. Shieh, and T. S. Li, “A High Performance VLSI Architecture Design for 10/100 Mbps Ethernet Switching Fabric,” Digest of Technical Papers, 1998.[7] M. C. Chen, I. J. Huang, and C. H. Chen, “Parameter MAC Unit Implementation,” Design Automation Conference, 2001.[8] M. D. Shieh, M. H. Shue, C. H. Chen, and H. F. Lo, “A systematic Approach for Parallel CRC Computations,” Journal of Information Science and Engineering, Vol.17, pp. 445-461, 2001.[9] T. B. Pei and C. Zukowski, “High-Speed Parallel CRC Circuits in VLSI,” Communications, IEEE Transactions on , Vol. 40 Issue: 4 , April 1992 [10] Intel, “M80C186 CHMOS HIGH INTEFRATION 16-BIT MICROPROCESSOR,” Data Sheet, Feb. 2000.[11] Rajesh Nair, Gerry Ryan and Farivar Farzaneh,“A Symbol Based Algorithm for Hardware Implementation of Cyclic Redundancy Check ( CRC )“, Bay NetWorks, INC.,Santa Clara, 95052, 1997.[12] Turbo86/Turbo186 Specification and Data Sheet, March, 2000.[13] VT86C100A PCI Fast Ethernet Controller Data Sheet, VIA Technologies, INC. Aug 31, 1997.[14]“R1320 FAST ETHERNET RISC PROCESSOR ”, Users Manual, RISC DSP Communication Semiconductor Co., Ltd Feb. 2002.[15]“ Practical Approaches to SOC Verification,”Guy Mosensoson Verisity Design, Inc.[16]Terminology by courtesy of Bob Morasse,”Effective use of various levels of system abstractions within a HW/SW co-verification development,”class 545 Embedded Systems Conference.[17] A. S. Tanenbaum, “Computer Networks,” 3rd, Prentice-Hall, INC., 1996.[18] 陳銘志,陳中和,“10/100 Mbps乙太網路橋接器之微架構設計和集線器系統之研製,”,第十三屆全國技術及職業教育研討會論文集,1998年5月。[19] 陳銘志,”10/100 Mbps乙太網路集線控制器之研製和效能量測”,雲林科技大學電子與資訊工程技術研究所碩士論文,1999年2月。[20] 黃能富,”區域網路與高速網路”,維科出版社,1998年6月。[21] DEC chip 21140 PCI Fast Ethernet LAN Controller Hardware Reference Manual, Version 2.1, Digital Equipment Corporation.[22] IEEE 802.3 CSMA/CD (ETHERNET) Home Page URL: http://grouper.ieee.org/groups/802/3/index.html

QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top