在訊號處理及壓縮的領域裡，小波理論是一門新興的學問，而且有日漸重要的趨勢。但是在硬體實作上，往往有較高的複雜度，特別是在二維小波轉換方面，為了達到高速的處理速度，如何設計出一個控制電路較簡單且快速之二維離散小波轉換架構是一個研究的方向。
本論文採用控制複雜度較低之金字塔演算法PA( Direct Pyramid Algorithm )來降低控制之複雜度，為了縮短計算的時間與減少硬體的使用，模組的內部採用多相分解技術的降頻濾波器，與採用係數摺疊的降頻濾波器分別組成列轉換部分與行轉換部分。並且為了更進一步的縮短計算時間，在硬體架構上使用了兩個轉換模組。第一個模組計算好的資料可以直接交由第二個模組進行轉換，所以第一二層的轉換幾乎可以在同時間進行，進而更加快了速度。
與其他架構相比，本架構由於採用了兩個模組，所以匯流排的利用率較高，又因為不做資料的穿插計算，所以控制複雜度較低，基於有規律資料流以及採用了多相分解技術的降頻濾波器，此一架構可以達到較短的計算時間(為平行濾波器轉換架構的0.5~0.55倍)。

Wavelet theory is a new developing subject and becomes more and more important in the field of signal processing and compression. In hardware implementations, especially two dimensional wavelet transform, Hence, it is difficult to implement it with hardware. For the purpose of high speed and low cost, it is a research subject to design a two dimensional discrete wavelet transform architecture which has a simple control circuit and high speed processing.
This paper adopts PA( Direct Pyramid Algorithm ) to reduce control complexity. In order to get high speed, we adopt polyphase decomposition decimation filters and coefficient folding decimation filters to form row transformation and column transformation respectively in the modules. To further reduce calculation time, we use two transformation modules, therefore, the calculated data from module one is directly passed to module two for transformation. Hence, the first and second level of transformations almost happen at the same time to speed up the processing.
In comparison with other architectures, this architecture has a higher bus utilization, and because there is no interleaving data calculation, it has lower control complexity. By means of regular data stream and adopting polyphase decomposition decimation filters, compare with the parallel filter architecture, this architecture achieves shorter calculation time (0.5~0.55 times of parallel filter architecture).

1. 緒論 1
2. 小波轉換理論與架構 7
2.1. 連續小波轉換 7
2.2. 離散小波轉換 10
2.3. 二維離散小波轉換 16
2.4. 二維離散小波轉換架構之介紹 19
3. 快速半遞迴二維離散小波轉換架構之設計 25
3.1. 系統架構 25
3.2. 濾波器製作的技術 27
3.2.1. 多相分解技術( POLYPHASE DECOMPOSITION TECHNIQUE ) 27
3.2.2. 係數摺疊技術( COEFFICIENT FOLDING TECHNIQUE ) 29
4. 效能分析與比較 37
5. 結論 39
參考文獻 40
附錄 43
電路設計 43

[1] Po-Cheng Wu and Liang-Gee Chen, “An efficient architecture for two-dimensional discrete wavelet transform,” IEEE Tran. on Circuits and Systems for Video Technology, Vol.11, pp.536 –545, April 2001.
[2] Po-Cheng Wu and Liang-Gee Chen, “An efficient architecture for two-dimensional discrete wavelet transform,” IEEE VLSI Technology, Systems, and Applications, pp.112-115, 1999
[3] Seung-Kwon Paek and Lee-Sup Kim, “2D DWT VLSI architecture for wavelet image processing,” IEEE Electronics Letters, vol.34, pp.537 –538, March 1998.
[4] Tay-Jyi Lin, Chein-Wei Jen, “An efficient 2-D architecture via resource cycling”, Circuits and Systems, vol. 4, pp. 914 –917, 2001
[5] 單維彰, 凌波初步, 全華, 台北市, 2000
[6] 繆紹綱, 數位影像處理 活用Matlab, 全華, 台北市, 2002
[7] D.Schlichtharle, Digital Filters Basics and Design, Springer, 2000
[8] C. Chakrabarti and M. Vishwanath, “Efficient realization of the discrete and continuous wavelet transforms: From single chip implementations to mappings on SIMD array computers,” IEEE Trans. Signal Processing, vol.43, pp.759-771, Mar, 1995.
[9] M. Vishwanath, R. M. Owens, and M. J. Irwin, “VLSI architectures for the discrete wavelet transform,” IEEE Trans. Circuits Syst. II, vol.42, pp.305-316, May, 1995.
[10] C. Chakrabarti and M. Vishwanath, “Architectures for wavelet transforms: A survey,” J. VLSI Signal Processing, vol.14, pp.171-192, 1996.
[11] Ming-Hwa Sheu, Shun-Fa Cheng and Ming-Der Shieh, “A pipelined VLSI Module Structure Design fir Discrete Wavelet Transforms,” IEEE Circuits and Systems, vol.4, pp.352 –355, 1996
[12] I, Daubechies, “Orthonormal bases of compactly supported wavelets,” Comm. Pure & Appl. Maths, vol. XLI, pp.909-916, 1988.
[13] D. Gabor, “Theory of communication,” J. IEEE, vol.93, pp.429-457, 1946.
[14] 陳同孝,張真誠,黃國峰, 數位影像處理技術, 松崗, 台北市, 2001
[15] 戴顯權, 資料壓縮, 松崗, 台北市, 2001
[16] 陳建宏, 多媒體導論, 全華, 台北市, 1998
[17] 廖裕評,陸瑞強, CPLD數位電路設計 使用Max+plus II入門篇, 全華, 台北市, 1999
[18] 廖裕評,陸瑞強, CPLD數位電路設計 使用Max+plus II應用篇, 全華, 台北市, 2001
[19] 張智星, MATLB程式設計與應用, 清蔚科技, 新竹市, 2000
[20] M. Vishwanath, “The recursive pyramid algorithm for the discrete wavelet transform,” IEEE Trans. Signal Processing., vol.42, no. 3, pp. 673-676, Mar. 1994.
[21] M. Vetterli, “Wavelet and filter banks: theory and design,” IEEE Trans. on Signal Processing, vol. 40, no. 9, pp. 2207-2232, Sep. 1992.
[22] O. Rioul, and M. Vetterli, “Wavelets and signal processing,” IEEE Signal Processing Mag., pp. 14-38, Oct. 1991.
[23] O. Rioul, and P. Duhamel, “Fast algorithms for discrete and continuous wavelet transforms,” IEEE Trans. Inform. Theory, vol 38, pp. 169-586, Mar. 1992.
[24] “MAX+PLUS II Programmable Logic Development System Getting Started,” Altera Co., 1995.
[25] A. S. Lewis and G. Knowles, “VLSI architecture for 2-D Daubechies wavelet transform without multipliers,” Electron. Lett., vol. 27, pp.171-173, Jan. 1991.
[26] C. Chakrabarti and C. Mumford, “Efficient realizations of analysis and syntheses filters based on the 2-D discrete wavelet transform,” in Proc. IEEE ICASSP, pp.3256-3259, May 1996.
[27] H. Y. H. chuang and L. Chen, “VLSI architecture for fast 2-D discrete orthonormal wavelet transform,” J. VLSI Signal Processing, vol. 10, pp.225-236, 1995.